Z80

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Zilog Z80A

The Z80 is an 8-bit microprocessor designed by Zilog founder and CEO Federico Faggin, first released in July 1976. It is the CPU used in the Amstrad CPC / Plus / PCW computers.

The Z80/Z80A was a very popular microprocessor, used in a wide range of applications, from gaming consoles like the ColecoVision, the Sega Master System and Sega GameGear to personal computers like the ZX81, ZX Spectrum and MSX.

It was used in the Commodore C128 as a secondary processor in order to achieve CP/M compatibility. Similarly, the Acorn Z80 Second Processor expansion for the BBC Micro enables CP/M compatibility.

The best-selling devices to feature a Zilog Z80 are the Sega MegaDrive with 40 million units sold Source, and the TI graphing calculators with 90 million units sold Source.

Although there were definitely other CPUs in use in the 1980s, the vast majority of microcomputers people had at home or at the office used either a MOS 6502 (or one of its variants), a Zilog Z80, an early member of the Intel 8086 family, or a Motorola 68000.


History

In the early 1970s, Intel developed the 8080, one of the first widely used microprocessors. However, a group of engineers led by Federico Faggin, the originator of the 8080 architecture in early 1972, left Intel to start their own company called Zilog in 1974.

At Zilog, Faggin and his team wanted to create an improved version of the Intel 8080 that would be more efficient, flexible, and easier to use. This led to the development of the Z80, which was designed to be both backward-compatible with the 8080 and more powerful. This compatibility meant that any software written for the 8080 could run on the Z80, making it an attractive upgrade for manufacturers and developers.

The Z80 had several key improvements over the 8080. It featured more registers, block instructions, bitwise ops, indexed addressing, and improved interrupt handling. It also had built-in memory refresh for dynamic RAM, that made it easier to build systems around it.


Description

The Z80 microprocessor is an 8-bit CPU with a 4-bit ALU and a 16-bit address bus capable of direct access to 64KB of memory space. The Z80 is a little-endian CPU, meaning it stores 16-bit values with the least significant byte first, followed by the most significant byte.

It has a language of 252 root instructions and with the reserved 4 bytes as prefixes, access to an additional 308 instructions. Although it lacks the raw processing power of processors like the Intel 80x86 or the Motorola 68000 series, the Z80 is extremely useful for low cost control applications.

The Z80 has about 8500 transistors. To put it into perspective, 64KB of DRAM contains 524288 transistors, as 1 bit of DRAM needs 1 transistor. Fun fact: an Amstrad CPC equipped with a 4MB RAM expansion has 32 million transistors dedicated to RAM while the Z80 CPU still has only 8500 transistors.

The Z80 is mid-1970s technology while the 64KB DRAM is early-1980s technology and the 4MB DRAM is early-1990s technology.

The Z80 comes in a 40-pin DIP package. It has been manufactured in A, B, and C models, differing only in maximum clock speed. It also has been manufactured as a stand-alone microcontroller with various configurations of on-chip RAM and EPROM.


Part numbers used in the Amstrad CPC

The Z80 CPU has been manufactured by others, and various Z80s have been used in the construction of the CPC during its lifetime:

All the Z80 CPUs that Amstrad used on CPC and Plus machines are NMOS. Source


Modern incarnations

Zilog ended the production of the Z80 in April 2024. This chip is still available in ample quantities through NOS chip suppliers and can be purchased for 1.20€. Source

Also, Zilog continues to produce the eZ80 which is a modernized Z80 CPU.

Apart from surplus/new Z80-clones that are quite easy to find, many emulations depend on software implementations of the Z80:


Registers

Register Size Description Notes
B, C, D, E, H, L 8-bit General-purpose registers Can form 16-bit pairs: BC, DE, HL
A (Accumulator) 8-bit Main register for arithmetic, logic, and data transfer Most used register
F (Flags) 8-bit
  • bit7 - SF - Sign Flag
  • bit6 - ZF - Zero Flag
  • bit5 - F5 - Undocumented by Zilog
  • bit4 - HF - Half Carry Flag
  • bit3 - F3 - Undocumented by Zilog
  • bit2 - PF - Parity Flag (also sometimes used for Overflow)
  • bit1 - NF - Negate Flag (last ALU op was subtract or compare)
  • bit0 - CF - Carry Flag
 Flags (including F5 and F3) are affected by most operations.

HF and NF are used in the DAA algorithm.

AF', BC', DE', HL' 16-bit Alternate register set Swappable with primary registers for fast context switching
SP (Stack Pointer) 16-bit Points to top of the stack Used for subroutine calls and interrupt handling
PC (Program Counter) 16-bit Points to the next instruction Automatically increments as instructions execute
IX, IY (Index Registers) 16-bit Used for indexed addressing Can be split into IXH/IXL, IYH/IYL for 8-bit access
I (Interrupt Vector) 8-bit Holds base address for interrupt mode 2 Combined with external data to form an interrupt vector
R (Memory Refresh) 8-bit Increments after each M1 cycle (instruction or prefix fetch) to refresh DRAM Only the lower 7 bits are incremented. Bit7 can only be changed by writing to the R register.


Internal State

Register Size Description Notes
IM (Interrupt Mode) 2-bit Specifies the interrupt mode (0, 1, or 2) Controls how interrupts are handled:
  • IM 0: External devices provide an opcode to execute (most likely an RST instruction). This mode was originally implemented in the Intel 8080 CPU
  • IM 1: Fixed vector at 0038h
  • IM 2: Vector provided by I register and external data

The NMI vector is fixed at 0066h, regardless of the I register, and of the IM interrupt mode.

IFF1 1-bit Main Interrupt Flip-Flop Set when interrupts are enabled, cleared on disable.

When the CPU accepts a maskable interrupt, both IFF1 and IFF2 are automatically cleared, inhibiting further interrupts.

IFF2 1-bit Stores the state of IFF1 during Non-Maskable Interrupts (NMI) When an NMI occurs, the processor clears IFF1 to disable interrupts temporarily.

IFF2 stores the previous state of IFF1 so that after the NMI is handled, IFF1 can be restored to its original state.

A barebone Amstrad CPC doesn't use NMI. So IFF1 and IFF2 are always the same. However, NMI is used by some expansions.

HALT 1-bit HALT state /HALT indicates that the CPU has executed a HALT instruction and is waiting for either an NMI or an IRQ (with IFF1 enabled) before operation can resume.

Each cycle in the HALT state is a normal M1 (fetch) cycle except that the data received from the memory is ignored and an NOP instruction is forced internally to the CPU. The purpose of executing NOP instructions while in the HALT state is to keep the memory refresh signals active.

WZ 16-bit Internal temporary register pair. Also known as MEMPTR Used for memory and address calculations.

Normally, you never see the content of this register. But it leaks through the flags F5 and F3 in the BIT b,(HL) instruction. Source

Q 8-bit Internal register where it assembles the new content of the F register, before moving it back to F 
 On Zilog NMOS Z80, when the instruction doesn't compute new flags, this register is cleared instead. But not on NEC NMOS Z80. And CMOS Z80 behave in a different way too.
 Normally, you never see the content of this register. But it leaks through F5 and F3 in the SCF/CCF instructions. Source
 Only 1 extra bit (F-changed) is needed for emulation Source. Also note that while POP AF and EX AF,AF' modify F, they do not compute new flag values. Source

The explanation above is just an approximation. In fact, SCF/CCF instructions are unstable. Source

As of Oct 2024, this is now fully understood. Everything happens due to the fact that two internal buses HBUS and LBUS, to which the contents of registers A and F are issued at the beginning of the instruction, respectively, at some point are electrically combined.

And in those bits where opposite values 0 and 1 are combined, a certain average potential appears, conditional 0.5. And then, these values are written back to the F register, and depending on the threshold of the transistor gates, these conditional 0.5 can turn into both 0 and 1. Source (RU)

IR (Instruction Register) 8-bit Holds the opcode of the currently executing instruction Internally used, not accessible by the programmer. Not to be confused with I (Interrupt Vector) and R (Memory Refresh) registers.
EIP (Extended Instruction Prefix) 2-bit Holds the prefix for extended instructions (CB, ED, or none) Used for extended instruction sets like bitwise ops.
IMP (Indexing Mode Prefix) 2-bit Specifies the indexing mode (DD for IX+d, FD for IY+d, or none for HL) Indicates use of index registers (IX or IY) for memory access.

Notes:

  • EIP and IMP can be fusioned into a 3-bit internal state as there are only 7 possible values for the prefixes (none, ed, dd, fd, cb, ddcb, fdcb). Probably not a win though as it makes everything more confusing.
  • IFF1 / IFF2 are called IEF1 / IEF2 (Interrupt Enable Flip-flops) in the Zilog eZ80 manual.


Addressing Modes

Many instructions, such as arithmetic instructions or loads, include more than one operand. In these cases, two different types of addressing can be employed in the same instruction.

For example, LD (HL),42 uses Immediate Addressing to specify the source and Register Indirect Addressing to specify the destination.


Instruction Execution Sequence

For an instruction to fully execute, the Z80 goes through these key phases in order:

  1. Prefix and Opcode Fetch (M1)
  2. Operand Fetch (if needed)
  3. Memory Read / I/O Read (if needed)
  4. Operation
  5. Memory Write / I/O Write (if needed)
  6. Loop (for block instructions only)
  7. At the end of every instruction, the IRQ (if IFF1 is active) and NMI pins are checked

For example, the instruction RL (IX+42) will execute as follow:

  1. M1 (4 t-states): Prefix fetch &DD then increment PC
  2. M1 (4 t-states): Opcode fetch &CB (the second prefix) then increment PC
  3. M2 (3 t-states): Operand fetch 42 (the displacement byte) then increment PC
  4. M3 (5 t-states): Operand fetch &16 (the real opcode) then increment PC, while calculating the address IX+42
  5. M4 (4 t-states): Memory read at address IX+42 then RL operation
  6. M5 (3 t-states): Memory write at address IX+42


Z80 Instructions

Legend

Notation Meaning Operand bits
d 8-bit signed relative offset dddddddd
e 16-bit relative address eeeeeeee
n 8-bit immediate nnnnnnnn
nn 16-bit address or immediate lolololo hihihihi

Flags

  • - = no change
  • + = change by definition (if noted, by the operation marked with '=> flags', otherwise by the only non-single-bit operation):
* S = sign, bit 7 of the result byte (accumulator or high byte for 16-bit operations)
* Z = zero, set if the result is zero (8 or 16-bit value)
* 5 = undocumented, bit 5 of the result byte
* H = half-carry, the carry (theoretical bit 4) of the low nibble of the result byte
* 3 = undocumented, bit 3 of the result byte
* P = parity (set if the result byte has an even number of bits set) or overflow (set when crossing the boundary of the signed range); always specified
* N = negative, set if the previous operation was a subtraction; always specified
* C = carry, the theoretical bit 8 of the result byte
  • 0 = always reset
  • 1 = always set
  • X = change described under effect
  • P = parity (only for the parity flag)
  • V = overflow (only for the parity flag)
  • A = OR with the respective bit of the accumulator
  • C = set if the counter (bc) is nonzero after decrementing

Registers

  • r,r̃: 000=B, 001=C, 010=D, 011=E, 100=H, 101=L, 111=A (110 is treated separately)
  • s,s̃: 000=B, 001=C, 010=D, 011=E, 100=IXH/IYH, 101=IXL/IYL, 111=A (110 is treated separately)
  • pp: 00=BC, 01=DE, 10=HL, 11=SP
  • p̃p̃: 00=BC, 01=DE, 10=HL, 11=AF
  • qq: 00=BC, 01=DE, 10=IX/IY, 11=SP
  • q̃q̃: 00=BC, 01=DE, 10=IX/IY, 11=AF

Miscellaneous

  • () = indirection
  • (()) = I/O port
  • [] = operator precedence (to avoid confusion with indirection)
  • e.b = the bth bit of the value of expression e
  • * = any bit value (0 or 1)
  • wz = an internal 16-bit register connected to 16-bit operations
  • tmp, tmp2 = temporary storage whose value is thrown away after each instruction

Load group

Instruction Opcode NOPs Cycles S Z 5 H 3 P N C Effect Description
ld r,r̃ 01rrrr̃r̃r̃ 1 4 (4) - - - - - - - - r := r̃ 8-bit Load
ld (hl),r 01110rrr 2 7 (4,3) (hl) := r
ld r,(hl) 01rrr110 2 7 (4,3) r := (hl)
ld s,s̃ DD/FD 01ssss̃s̃s̃ 2 8 (4,4) s := s̃
ld (ixy+d),r DD/FD 01110rrr dddddddd 5 19 (4,4,3,5,3) (ixy+d) := r
ld r,(ixy+d) DD/FD 01rrr110 dddddddd 5 19 (4,4,3,5,3) r := (ixy+d)
ld r,n 00rrr110 nnnnnnnn 2 7 (4,3) r := n
ld (hl),n 00110110 nnnnnnnn 3 10 (4,3,3) (hl) := n
ld (ixy+d),n DD/FD 00110110 dddddddd nnnnnnnn 6 19 (4,4,3,5,3) (ixy+d) := n
ld (bc),a 00000010 2 7 (4,3) (bc) := a
ld a,(bc) 00001010 2 7 (4,3) a := (bc)
ld (de),a 00010010 2 7 (4,3) (de) := a
ld a,(de) 00011010 2 7 (4,3) a := (de)
ld (nn),a 00110010 lolololo hihihihi 4 13 (4,3,3,3) (nn) := a
ld a,(nn) 00111010 lolololo hihihihi 4 13 (4,3,3,3) a := (nn)
ld pp,nn 00pp0001 lolololo hihihihi 3 10 (4,3,3) - - - - - - - - pp := nn 16-bit Load
ld qq,nn DD/FD 00qq0001 lolololo hihihihi 4 14 (4,4,3,3) qq := nn
ld (nn),hl 00100010 lolololo hihihihi 5 16 (4,3,3,3,3) (nn) := hl
ld (nn),ixy DD/FD 00100010 lolololo hihihihi 6 20 (4,4,3,3,3,3) (nn) := ixy
ld (nn),pp ED 01pp0011 lolololo hihihihi 6 20 (4,4,3,3,3,3) (nn) := pp
ld hl,(nn) 00101010 lolololo hihihihi 5 16 (4,3,3,3,3) hl := (nn)
ld ixy,(nn) DD/FD 00101010 lolololo hihihihi 6 20 (4,4,3,3,3,3) ixy := (nn)
ld pp,(nn) ED 01pp1011 lolololo hihihihi 6 20 (4,4,3,3,3,3) pp := (nn)
ld sp,hl 11111001 2 6 (6) sp := hl
ld sp,ixy DD/FD 11111001 3 10 (4,6) sp := ixy
pop p̃p̃ 11p̃p̃0001 3 10 (4,3,3) - - - - - - - - p̃p̃ := (sp), sp += 2 Pop a value from the stack
pop q̃q̃ DD/FD 11q̃q̃0001 4 14 (4,4,3,3) q̃q̃ := (sp), sp += 2
push p̃p̃ 11p̃p̃0101 4 11 (5,3,3) - - - - - - - - sp -= 2, (sp) := p̃p̃ Push a value onto the stack
push q̃q̃ DD/FD 11q̃q̃0101 5 15 (4,5,3,3) sp -= 2, (sp) := q̃q̃

16-bit Arithmetic group

Instruction Opcode NOPs Cycles S Z 5 H 3 P N C Effect Description
inc pp 00pp0011 2 6 (6) - - - - - - - - pp += 1 Increment
inc qq DD/FD 00qq0011 3 10 (4,6) qq += 1
dec pp 00pp1011 2 6 (6) - - - - - - - - pp -= 1 Decrement
dec qq DD/FD 00qq1011 3 10 (4,6) qq -= 1
add hl,pp 00pp1001 3 11 (4,4,3) - - + + + - 0 + hl += pp Add
add ixy,qq DD/FD 00qq1001 4 15 (4,4,4,3) ixy += qq
adc hl,qq ED 01qq1010 4 15 (4,4,4,3) + + + + + V 0 + hl += qq + cf Add with Carry
sbc hl,qq ED 01qq0010 4 15 (4,4,4,3) + + + + + V 1 + hl -= qq + cf Subtract with Carry

8-bit ALU group

Instruction Opcode NOPs Cycles S Z 5 H 3 P N C Effect Description
inc r 00rrr100 1 4 (4) + + + + + V 0 - r += 1 Increment
inc s DD/FD 00sss100 2 8 (4,4) s += 1
inc (hl) 00110100 3 11 (4,4,3) (hl) += 1
inc (ixy+d) DD/FD 00110100 dddddddd 6 23 (4,4,3,5,4,3) (ixy+d) += 1
dec r 00rrr101 1 4 (4) + + + + + V 1 - r -= 1 Decrement
dec s DD/FD 00sss101 2 8 (4,4) s -= 1
dec (hl) 00110101 3 11 (4,4,3) (hl) -= 1
dec (ixy+d) DD/FD 00110101 dddddddd 6 23 (4,4,3,5,4,3) (ixy+d) -= 1
add a,n 11000110 nnnnnnnn 2 7 (4,3) + + + + + V 0 + a += n Add
add a,r 10000rrr 1 4 (4) a += r
add a,s DD/FD 10000sss 2 8 (4,4) a += s
add a,(hl) 10000110 2 7 (4,3) a += (hl)
add a,(ixy+d) DD/FD 10000110 dddddddd 5 19 (4,4,3,5,3) a += (ixy+d)
adc a,n 11001110 nnnnnnnn 2 7 (4,3) + + + + + V 0 + a += n + cf Add with Carry
adc a,r 10001rrr 1 4 (4) a += r + cf
adc a,s DD/FD 10001sss 2 8 (4,4) a += s + cf
adc a,(hl) 10001110 2 7 (4,3) a += (hl) + cf
adc a,(ixy+d) DD/FD 10001110 dddddddd 5 19 (4,4,3,5,3) a += (ixy+d) + cf
sub n 11010110 nnnnnnnn 2 7 (4,3) + + + + + V 1 + a -= n Subtract
sub r 10010rrr 1 4 (4) a -= r
sub s DD/FD 10010sss 2 8 (4,4) a -= s
sub (hl) 10010110 2 7 (4,3) a -= (hl)
sub (ixy+d) DD/FD 10010110 dddddddd 5 19 (4,4,3,5,3) a -= (ixy+d)
sbc a,n 11011110 nnnnnnnn 2 7 (4,3) + + + + + V 1 + a -= n + cf Subtract with Carry
sbc a,r 10011rrr 1 4 (4) a -= r + cf
sbc a,s DD/FD 10011sss 2 8 (4,4) a -= s + cf
sbc a,(hl) 10011110 2 7 (4,3) a -= (hl) + cf
sbc a,(ixy+d) DD/FD 10011110 dddddddd 5 19 (4,4,3,5,3) a -= (ixy+d) + cf
and n 11100110 nnnnnnnn 2 7 (4,3) + + + 1 + P 0 0 a := a and n Logical AND
and r 10100rrr 1 4 (4) a := a and r
and s DD/FD 10100sss 2 8 (4,4) a := a and s
and (hl) 10100110 2 7 (4,3) a := a and (hl)
and (ixy+d) DD/FD 10100110 dddddddd 5 19 (4,4,3,5,3) a := a and (ixy+d)
xor n 11101110 nnnnnnnn 2 7 (4,3) + + + 0 + P 0 0 a := a xor n Logical eXclusive OR
xor r 10101rrr 1 4 (4) a := a xor r
xor s DD/FD 10101sss 2 8 (4,4) a := a xor s
xor (hl) 10101110 2 7 (4,3) a := a xor (hl)
xor (ixy+d) DD/FD 10101110 dddddddd 5 19 (4,4,3,5,3) a := a xor (ixy+d)
or n 11110110 nnnnnnnn 2 7 (4,3) + + + 0 + P 0 0 a := a or n Logical Inclusive OR
or r 10110rrr 1 4 (4) a := a or r
or s DD/FD 10110sss 2 8 (4,4) a := a or s
or (hl) 10110110 2 7 (4,3) a := a or (hl)
or (ixy+d) DD/FD 10110110 dddddddd 5 19 (4,4,3,5,3) a := a or (ixy+d)
cp n 11111110 nnnnnnnn 2 7 (4,3) + + X + X V 1 + tmp := a - n, f5 := n.5, f3 := n.3 Compare
cp r 10111rrr 1 4 (4) tmp := a - r, f5 := r.5, f3 := r.3
cp s DD/FD 10111sss 2 8 (4,4) tmp := a - s, f5 := s.5, f3 := s.3
cp (hl) 10111110 2 7 (4,3) tmp := a - (hl), f5 := (hl).5, f3 := (hl).3
cp (ixy+d) DD/FD 10111110 dddddddd 5 19 (4,4,3,5,3) tmp := a - (ixy+d), f5 := (ixy+d).5, f3 := (ixy+d).3

BCD group

Instruction Opcode NOPs Cycles S Z 5 H 3 P N C Effect Description
daa 00100111 1 4 (4) + + + X + P - X tmp := a,

if nf then 

if hf or [a and 0x0f > 9] then tmp -= 0x06
if cf or [a > 0x99] then tmp -= 0x60

else 

if hf or [a and 0x0f > 9] then tmp += 0x06
if cf or [a > 0x99] then tmp += 0x60

endif,

tmp => flags, cf := cf or [a > 0x99],

hf := a.4 xor tmp.4, a := tmp

Decimal Adjust Accumulator
rrd ED 01100111 5 18 (4,4,3,4,3) + + + 0 + P 0 - tmp := (hl), (hl) := [tmp >> 4] + [[a and 0x0f] << 4],

a := [a and 0xf0] + [tmp and 0x0f] => flags

Rotate Right Decimal
rld ED 01101111 5 18 (4,4,3,4,3) + + + 0 + P 0 - tmp := [(hl) << 4] + [a and 0x0f], (hl) := tmp,

a := [a and 0xf0] + [tmp >> 8] => flags

Rotate Left Decimal

ROT group

Instruction Opcode NOPs Cycles S Z 5 H 3 P N C Effect Description
rlca 00000111 1 4 (4) - - + 0 + - 0 X cf := a.7, a := [a << 1] + cf Fast Rotate
rrca 00001111 1 4 (4) cf := a.0, a := [a >> 1] + [cf << 7]
rla 00010111 1 4 (4) ocf := cf, cf := a.7, a := [a << 1] + ocf
rra 00011111 1 4 (4) ocf := cf, cf := a.0, a := [a >> 1] + [ocf << 7]
rl r CB 00010rrr 2 8 (4,4) + + + 0 + P 0 X ocf := cf, cf := r.7, r := [r << 1] + ocf Rotate Left
rl (hl) CB 00010110 4 15 (4,4,4,3) ocf := cf, cf := (hl).7, (hl) := [(hl) << 1] + ocf
rl (ixy+d) DD/FD CB dddddddd 00010110 7 23 (4,4,3,5,4,3) ocf := cf, cf := (ixy+d).7, (ixy+d) := [(ixy+d) << 1] + ocf
rl (ixy+d)->r DD/FD CB dddddddd 00010rrr 7 23 (4,4,3,5,4,3) ocf := cf, cf := (ixy+d).7, (ixy+d) := r := [(ixy+d) << 1] + ocf
rlc r CB 00000rrr 2 8 (4,4) + + + 0 + P 0 X cf := r.7, r := [r << 1] + cf Rotate Left Carry
rlc (hl) CB 00000110 4 15 (4,4,4,3) cf := (hl).7, (hl) := [(hl) << 1] + cf
rlc (ixy+d) DD/FD CB dddddddd 00000110 7 23 (4,4,3,5,4,3) cf := (ixy+d).7, (ixy+d) := [(ixy+d) << 1] + cf
rlc (ixy+d)->r DD/FD CB dddddddd 00000rrr 7 23 (4,4,3,5,4,3) cf := (ixy+d).7, (ixy+d) := r := [(ixy+d) << 1] + cf
rr r CB 00011rrr 2 8 (4,4) + + + 0 + P 0 X ocf := cf, cf := r.0, r := [r >> 1] + [ocf << 7] Rotate Right
rr (hl) CB 00011110 4 15 (4,4,4,3) ocf := cf, cf := (hl).0, (hl) := [(hl) >> 1] + [ocf << 7]
rr (ixy+d) DD/FD CB dddddddd 00011110 7 23 (4,4,3,5,4,3) ocf := cf, cf := (ixy+d).0, (ixy+d) := [(ixy+d) >> 1] + [ocf << 7]
rr (ixy+d)->r DD/FD CB dddddddd 00011rrr 7 23 (4,4,3,5,4,3) ocf := cf, cf := (ixy+d).0, (ixy+d) := r := [(ixy+d) >> 1] + [ocf << 7]
rrc r CB 00001rrr 2 8 (4,4) + + + 0 + P 0 X cf := r.0, r := [r >> 1] + [cf << 7] Rotate Right Carry
rrc (hl) CB 00001110 4 15 (4,4,4,3) cf := (hl).0, (hl) := [(hl) >> 1] + [cf << 7]
rrc (ixy+d) DD/FD CB dddddddd 00001110 7 23 (4,4,3,5,4,3) cf := (ixy+d).0, (ixy+d) := [(ixy+d) >> 1] + [cf << 7]
rrc (ixy+d)->r DD/FD CB dddddddd 00001rrr 7 23 (4,4,3,5,4,3) cf := (ixy+d).0, (ixy+d) := r := [(ixy+d) >> 1] + [cf << 7]
sla r CB 00100rrr 2 8 (4,4) + + + 0 + P 0 X cf := r.7, r := r << 1 Shift Left Arithmetic
sla (hl) CB 00100110 4 15 (4,4,4,3) cf := (hl).7, (hl) := (hl) << 1
sla (ixy+d) DD/FD CB dddddddd 00100110 7 23 (4,4,3,5,4,3) cf := (ixy+d).7, (ixy+d) := (ixy+d) << 1
sla (ixy+d)->r DD/FD CB dddddddd 00100rrr 7 23 (4,4,3,5,4,3) cf := (ixy+d).7, (ixy+d) := r := (ixy+d) << 1
sra r CB 00101rrr 2 8 (4,4) + + + 0 + P 0 X cf := r.0, r := r >> 1, r.7 := r.6 Shift Right Arithmetic
sra (hl) CB 00101110 4 15 (4,4,4,3) cf := (hl).0, (hl) := (hl) >> 1, (hl).7 := (hl).6
sra (ixy+d) DD/FD CB dddddddd 00101110 7 23 (4,4,3,5,4,3) cf := (ixy+d).0, (ixy+d) := (ixy+d) >> 1, (ixy+d).7 := (ixy+d).6
sra (ixy+d)->r DD/FD CB dddddddd 00101rrr 7 23 (4,4,3,5,4,3) cf := (ixy+d).0, tmp := (ixy+d) >> 1, tmp.7 := tmp.6, (ixy+d) := r := tmp
sll r CB 00110rrr 2 8 (4,4) + + + 0 + P 0 X cf := r.7, r := [r << 1] + 1 Shift Left Logical
sll (hl) CB 00110110 4 15 (4,4,4,3) cf := (hl).7, (hl) := [(hl) << 1] + 1
sll (ixy+d) DD/FD CB dddddddd 00110110 7 23 (4,4,3,5,4,3) cf := (ixy+d).7, (ixy+d) := [(ixy+d) << 1] + 1
sll (ixy+d)->r DD/FD CB dddddddd 00110rrr 7 23 (4,4,3,5,4,3) cf := (ixy+d).7, (ixy+d) := r := [(ixy+d) << 1] + 1
srl r CB 00111rrr 2 8 (4,4) 0 + + 0 + P 0 X cf := r.0, r := r >> 1 Shift Right Logical
srl (hl) CB 00111110 4 15 (4,4,3) cf := (hl).0, (hl) := (hl) >> 1
srl (ixy+d) DD/FD CB dddddddd 00111110 7 23 (4,4,3,5,4,3) cf := (ixy+d).0, (ixy+d) := (ixy+d) >> 1
srl (ixy+d)->r DD/FD CB dddddddd 00111rrr 7 23 (4,4,3,5,4,3) cf := (ixy+d).0, (ixy+d) := r := (ixy+d) >> 1

Bitwise group

Instruction Opcode NOPs Cycles S Z 5 H 3 P N C Effect Description
bit b,r CB 01bbbrrr 2 8 (4,4) + + + 1 + P 0 - tmp := r and [1 << b] Test Bit
bit b,(hl) CB 01bbb110 3 12 (4,4,4) + + X 1 X P 0 - tmp := (hl) and [1 << b],

f5 := wz.13, f3 := wz.11

bit b,(ixy+d) DD/FD CB dddddddd 01bbb*** 6 20 (4,4,3,5,4) + + X 1 X P 0 - tmp := (ixy+d) and [1 << b],

f5 := [ixy+d].13, f3 := [ixy+d].11

res b,r CB 10bbbrrr 2 8 (4,4) - - - - - - - - r := r and ~[1 << b] Reset Bit
res b,(hl) CB 10bbb110 4 15 (4,4,4,3) (hl) := (hl) and ~[1 << b]
res b,(ixy+d) DD/FD CB dddddddd 10bbb110 7 23 (4,4,3,5,4,3) (ixy+d) := (ixy+d) and ~[1 << b]
res b,(ixy+d)->r DD/FD CB dddddddd 10bbbrrr 7 23 (4,4,3,5,4,3) (ixy+d) := r := (ixy+d) and ~[1 << b]
set b,r CB 11bbbrrr 2 8 (4,4) - - - - - - - - r := r or [1 << b] Set Bit
set b,(hl) CB 11bbb110 4 15 (4,4,4,3) (hl) := (hl) or [1 << b]
set b,(ixy+d) DD/FD CB dddddddd 11bbb110 7 23 (4,4,3,5,4,3) (ixy+d) := (ixy+d) or [1 << b]
set b,(ixy+d)->r DD/FD CB dddddddd 11bbbrrr 7 23 (4,4,3,5,4,3) (ixy+d) := r := (ixy+d) or [1 << b]
cpl 00101111 1 4 (4) - - + 1 + - 1 - a := ~a Complement
neg ED 01***100 2 8 (4,4) + + + + + V 1 + a := - a Negate

Block group

Instruction Opcode NOPs Cycles S Z 5 H 3 P N C Effect Description
ldir ED 10110000 6/5 21/16 (4,4,3,5,5)/(4,4,3,5) - - X 0 X C 0 - ldi, if bc <> 0 then pc -= 2 Block Load
lddr ED 10111000 6/5 21/16 (4,4,3,5,5)/(4,4,3,5) ldd, if bc <> 0 then pc -= 2
ldi ED 10100000 5 16 (4,4,3,5) tmp := (hl), (de) := tmp, de += 1, hl += 1,

bc -= 1, f5 := [tmp + a].1, f3 := [tmp + a].3

ldd ED 10101000 5 16 (4,4,3,5) tmp := (hl), (de) := tmp, de -= 1, hl -= 1,

bc -= 1, f5 := [tmp + a].1, f3 := [tmp + a].3

cpir ED 10110001 6/4 21/16 (4,4,3,5,5)/(4,4,3,5) + + X + X C 1 - cpi, if bc <> 0 and nz then pc -= 2 Block Compare
cpdr ED 10111001 6/4 21/16 (4,4,3,5,5)/(4,4,3,5) cpd, if bc <> 0 and nz then pc -= 2
cpi ED 10100001 4 16 (4,4,3,5) tmp := a - (hl) => flags, bc -= 1, hl += 1,

f5 := [tmp - hf].1, f3 = [tmp - hf].3

cpd ED 10101001 4 16 (4,4,3,5) tmp := a - (hl) => flags, bc -= 1, hl -= 1,

f5 := [tmp - hf].1, f3 = [tmp - hf].3

inir ED 10110010 6/5 21/16 (4,5,4,3,5)/(4,5,4,3) + + + X + X X X ini, if b <> 0 then pc -= 2 Block I/O Input
indr ED 10111010 6/5 21/16 (4,5,4,3,5)/(4,5,4,3) ind, if b <> 0 then pc -= 2
ini ED 10100010 5 16 (4,5,4,3) tmp := ((c)), (hl) := tmp, hl += 1,

b -= 1 => flags, nf := tmp.7,

tmp2 := tmp + [[c + 1] and 0xff],

pf := parity of [[tmp2 and 0x07] xor b],

hf := cf := tmp2 > 255

ind ED 10101010 5 16 (4,5,4,3) tmp := ((c)), (hl) := tmp, hl -= 1,

b -= 1 => flags, nf := tmp.7,

tmp2 = tmp + [[c - 1] and 0xff],

pf := parity of [[tmp2 and 0x07] xor b],

hf := cf := tmp2 > 255

otir ED 10110011 6/5 21/16 (4,5,3,4,5)/(4,5,3,4) + + + X + X X X outi, if b <> 0 then pc -= 2 Block I/O Output
otdr ED 10111011 6/5 21/16 (4,5,3,4,5)/(4,5,3,4) outd, if b <> 0 then pc -= 2
outi ED 10100011 5 16 (4,5,3,4) tmp := (hl), ((c)) := tmp, hl += 1,

b -= 1 => flags, nf := tmp.7, tmp2 = tmp + l,

pf := parity of [[tmp2 and 0x07] xor b],

hf := cf := tmp2 > 255

outd ED 10101011 5 16 (4,5,3,4) tmp := (hl), ((c)) := tmp, hl -= 1,

b -= 1 => flags, nf := tmp.7, tmp2 = tmp + l,

pf := parity of [[tmp2 and 0x07] xor b],

hf := cf := tmp2 > 255

note: The INI instruction has incorrect timing in the official Zilog manual. Source

I/O group

Instruction Opcode NOPs Cycles S Z 5 H 3 P N C Effect Description
in a,(n) 11011011 nnnnnnnn 3 11 (4,3,4) - - - - - - - - a := ((n)) I/O Input
in r,(c) ED 01rrr000 4 12 (4,4,4) + + + 0 + P 0 - r := ((c))
in f,(c) ED 01110000 4 12 (4,4,4) + + + 0 + P 0 - tmp := ((c))
out (n),a 11010011 nnnnnnnn 3 11 (4,3,4) - - - - - - - - ((n)) := a I/O Output
out (c),r ED 01rrr001 4 12 (4,4,4) - - - - - - - - ((c)) := r
out (c),0 ED 01110001 4 12 (4,4,4) - - - - - - - - ((c)) := 0 (255 on CMOS CPU)

Control flow group

Instruction Opcode NOPs Cycles S Z 5 H 3 P N C Effect Description
rst t 11ttt111 4 11 (5,3,3) - - - - - - - - sp -= 2, (sp) := pc, pc := t Restart

ttt: 000=#0, 001=#8, 010=#10, 011=#18, 100=#20, 101=#28, 110=#30, 111=#38

call nn 11001101 lolololo hihihihi 5 17 (4,3,4,3,3) sp -= 2, (sp) := pc, pc := nn Call
call cc,nn 11ccc100 lolololo hihihihi 5/3 17/10 (4,3,4,3,3)/(4,3,3) if cc then sp -= 2, (sp) := pc, pc := nn Conditional call

ccc: 000=NZ, 001=Z, 010=NC, 011=C, 100=PO, 101=PE, 110=P, 111=M

jp nn 11000011 lolololo hihihihi 3 10 (4,3,3) - - - - - - - - pc := nn Jump
jp (hl) 11101001 1 4 (4) pc := hl
jp (ixy) DD/FD 11101001 2 8 (4,4) pc := ixy
jp cc,nn 11ccc010 lolololo hihihihi 3 10 (4,3,3) if cc then pc := nn Conditional jump

ccc: 000=NZ, 001=Z, 010=NC, 011=C, 100=PO, 101=PE, 110=P, 111=M

jr e 00011000 eeeeeeee 3 12 (4,3,5) - - - - - - - - pc += e Relative jump
jr cc,e 001cc000 eeeeeeee 3/2 12/7 (4,3,5)/(4,3) if cc then pc += e Conditional relative jump

cc: 00=NZ, 01=Z, 10=NC, 11=C

djnz e 00010000 eeeeeeee 4/3 13/8 (5,3,5)/(5,3) b -= 1, if b <> 0 then pc += e Decrement, Jump Non-Zero
ret 11001001 3 10 (4,3,3) - - - - - - - - pc := (sp), sp += 2 Return
ret cc 11ccc000 4/2 11/5 (5,3,3)/(5) if cc then pc := (sp), sp += 2 Conditional return

ccc: 000=NZ, 001=Z, 010=NC, 011=C, 100=PO, 101=PE, 110=P, 111=M

reti ED 01001101 4 14 (4,4,3,3) pc := (sp), sp += 2, iff1 := iff2 Return from Interrupt
retn ED 01***101 4 14 (4,4,3,3) pc := (sp), sp += 2, iff1 := iff2 Return from NMI

CPU control group

Instruction Opcode NOPs Cycles S Z 5 H 3 P N C Effect Description
ld i,a ED 01000111 3 9 (4,5) - - - - - - - - i := a CPU State Load
ld r,a ED 01001111 3 9 (4,5) - - - - - - - - r := a
ld a,i ED 01010111 3 9 (4,5) + + + 0 + X 0 - a := i, pf := iff2
ld a,r ED 01011111 3 9 (4,5) + + + 0 + X 0 - a := r, pf := iff2
di 11110011 1 4 (4) - - - - - - - - iff1 := 0, iff2 := 0 Disable Interrupts
ei 11111011 1 4 (4) - - - - - - - - iff1 := 1, iff2 := 1 after the next instruction Enable Interrupts
im m ED 01mmm110 2 8 (4,4) - - - - - - - - im := m Set Interrupt Mode

mmm: 000=0, 001=0, 010=1, 011=2, 100=0, 101=0, 110=1, 111=2

halt 01110110 1 4 (4) - - - - - - - - wait for interrupt Suspends CPU operation
nop 00000000 1 4 (4) - - - - - - - - nothing No Operation
scf 00110111 1 4 (4) - - A 0 A - 0 1 nothing else Set Carry Flag
ccf 00111111 1 4 (4) - - A X A - 0 X hf := cf, cf := ~cf Complement Carry Flag
exx 11011001 1 4 (4) - - - - - - - - bc, de, hl <=> bc', de', hl' Exchange
ex de,hl 11101011 1 4 (4) - - - - - - - - de <=> hl
ex (sp),hl 11100011 6 19 (4,3,4,3,5) - - - - - - - - (sp) <=> hl
ex (sp),ixy DD/FD 11100011 7 23 (4,4,3,4,3,5) - - - - - - - - (sp) <=> ixy
ex af,af' 00001000 1 4 (4) X X X X X X X X af <=> af'


M-cycles and T-states

In the Z80, M-cycles represent high-level execution cycles for an instruction, while T-states are individual clock cycles. Each M-cycle consists of several T-states, and instructions require one or more M-cycles.

M-cycles can be classified as follows:

  • Opcode Fetch (aka M1 cycle): this is always the first (and sometimes only) machine cycle in an instruction (4 clock cycles)
  • Memory Read: read a byte from memory (3 clock cycles)
  • Memory Write: write a byte to memory (3 clock cycles)
  • IO Read: read a byte from an IO port (4 clock cycles)
  • IO Write: write a byte to an IO port (4 clock cycles)
  • Interrupt Acknowledge: these are special machine cycles which are executed at the start of maskable interrupt handling
  • Extra: many instructions contain extra clock cycles necessary for computations. In the official CPU documentation, these are sometimes identified as separate machine cycles, and sometimes just lumped together with other machine cycle types.

The CALL cc,nn instruction is an example where an extra clock cycle is inserted in M3 depending if cc is true or not.


CPC Timings

On MSX, bus arbitration only applies to M1 machine cycles but access to VRAM has other limitations. On ZX Spectrum, bus arbitration is done not by using the /WAIT pin but by disabling the CPU clock when needed.

On CPC, bus arbitration occurs on every CPU bus access. The Gate Array asserts the /WAIT pin on the Z80 for 3 out of every 4 cycles, effectively aligning all operations to a 4-tick cycle. The Z80 extends T2 indefinitely by adding wait states until /WAIT is released.

The NOPs column corresponds to CPC timings, which account for the bus arbitration. The NOP instruction takes 4 cycles. This is the minimum amount of cycles an instruction can take.

Every M-cycle that involves a memory or I/O access will stretch the previous M-cycle due to bus arbitration. But beware, some M-cycles are purely internal and don't involve a memory or I/O access. So those won't stretch the previous M-cycle.

Nevertheless, a few CPC timings can appear surprising at first glance:

  • Instructions LD (IX+d),r and LD (IX+d),n take 5 and 6 NOPs respectively, even though they are both listed as 19 (4,4,3,5,3) cycles in the datasheet. This happens because LD (IX+d),r has one less memory access operation to do compared to LD (IX+d),n as it does not have to fetch its operand from memory.
  • Instructions IN r,(C) and OUT (C),r take 4 NOPs with CPC timings, even though they are listed as 12 (4,4,4) cycles in the datasheet. This happens because I/O access is not aligned with memory access. On Zilog manual, it is precised that one wait-state TW is automatically inserted after T2 on I/O access.

The CPC timings of some instructions will be altered if an interrupt happens. The interrupt test occurs on the last T-state of the instruction, and if it's low, the Z80 will insert 2 wait states to acknowledge the interrupt.

So, instructions which end in the third or fourth T-state relative to the read alignment for the next instruction fetch will be delayed by an extra 4 T-states. The few instructions which end in the first or second T-state won't since the first instruction fetch/read in the interrupt won't be delayed an extra 4 T-states. Source


Opcodes

The Z80 follows a 2-3-3 opcode bit pattern. Register instructions normally use three bits to specify the register used: 000=B, 001=C, 010=D, 011=E, 100=H, 101=L, 110=indirect through HL, 111=A.

Register pairs are encoded as: 00=BC, 01=DE, 10=HL, 11=SP. The PUSH and POP instructions use a slightly different encoding: 00=BC, 01=DE, 10=HL, 11=AF.

Three bits are used to specify condition codes: 000=NZ (Non Zero), 001=Z (Zero), 010=NC (Non Carry), 011=C (Carry), 100=PO (Parity Odd), 101=PE (Parity Even), 110=P (Plus), 111=M (Minus). The JR instruction only decodes the 2 lower bits of the condition code.

Condition C (carry) is unrecognizable from register C. To recognize which it is, conditions (flags) are used only in instructions: CALL, JR, JP, RET.

All CB-prefixed opcodes and half of the standard opcodes (from &40 to &BF) follow a strict uniform layout. The sole exception is the HALT instruction (opcode &76), which replaces the expected LD (HL),(HL) instruction.

The rest of the opcode table is also neatly organised but in a horizontal way instead of vertical.

Any instruction in bold is undocumented by Zilog.

Standard opcodes

Opcode Mnemonic
00 NOP
01 xx xx LD BC,nn
02 LD (BC),A
03 INC BC
04 INC B
05 DEC B
06 xx LD B,n
07 RLCA
Opcode Mnemonic
08 EX AF,AF'
09 ADD HL,BC
0A LD A,(BC)
0B DEC BC
0C INC C
0D DEC C
0E xx LD C,n
0F RRCA
Opcode Mnemonic
10 xx DJNZ e
11 xx xx LD DE,nn
12 LD (DE),A
13 INC DE
14 INC D
15 DEC D
16 xx LD D,n
17 RLA
Opcode Mnemonic
18 xx JR e
19 ADD HL,DE
1A LD A,(DE)
1B DEC DE
1C INC E
1D DEC E
1E xx LD E,n
1F RRA
Opcode Mnemonic
20 xx JR NZ,e
21 xx xx LD HL,nn
22 xx xx LD (nn),HL
23 INC HL
24 INC H
25 DEC H
26 xx LD H,n
27 DAA
Opcode Mnemonic
28 xx JR Z,e
29 ADD HL,HL
2A xx xx LD HL,(nn)
2B DEC HL
2C INC L
2D DEC L
2E xx LD L,n
2F CPL
Opcode Mnemonic
30 xx JR NC,e
31 xx xx LD SP,nn
32 xx xx LD (nn),A
33 INC SP
34 INC (HL)
35 DEC (HL)
36 xx LD (HL),n
37 SCF
Opcode Mnemonic
38 xx JR C,e
39 ADD HL,SP
3A xx xx LD A,(nn)
3B DEC SP
3C INC A
3D DEC A
3E xx LD A,n
3F CCF
Opcode Mnemonic
40 LD B,B
41 LD B,C
42 LD B,D
43 LD B,E
44 LD B,H
45 LD B,L
46 LD B,(HL)
47 LD B,A
Opcode Mnemonic
48 LD C,B
49 LD C,C
4A LD C,D
4B LD C,E
4C LD C,H
4D LD C,L
4E LD C,(HL)
4F LD C,A
Opcode Mnemonic
50 LD D,B
51 LD D,C
52 LD D,D
53 LD D,E
54 LD D,H
55 LD D,L
56 LD D,(HL)
57 LD D,A
Opcode Mnemonic
58 LD E,B
59 LD E,C
5A LD E,D
5B LD E,E
5C LD E,H
5D LD E,L
5E LD E,(HL)
5F LD E,A
Opcode Mnemonic
60 LD H,B
61 LD H,C
62 LD H,D
63 LD H,E
64 LD H,H
65 LD H,L
66 LD H,(HL)
67 LD H,A
Opcode Mnemonic
68 LD L,B
69 LD L,C
6A LD L,D
6B LD L,E
6C LD L,H
6D LD L,L
6E LD L,(HL)
6F LD L,A
Opcode Mnemonic
70 LD (HL),B
71 LD (HL),C
72 LD (HL),D
73 LD (HL),E
74 LD (HL),H
75 LD (HL),L
76 HALT
77 LD (HL),A
Opcode Mnemonic
78 LD A,B
79 LD A,C
7A LD A,D
7B LD A,E
7C LD A,H
7D LD A,L
7E LD A,(HL)
7F LD A,A
Opcode Mnemonic
80 ADD A,B
81 ADD A,C
82 ADD A,D
83 ADD A,E
84 ADD A,H
85 ADD A,L
86 ADD A,(HL)
87 ADD A,A
Opcode Mnemonic
88 ADC A,B
89 ADC A,C
8A ADC A,D
8B ADC A,E
8C ADC A,H
8D ADC A,L
8E ADC A,(HL)
8F ADC A,A
Opcode Mnemonic
90 SUB B
91 SUB C
92 SUB D
93 SUB E
94 SUB H
95 SUB L
96 SUB (HL)
97 SUB A
Opcode Mnemonic
98 SBC A,B
99 SBC A,C
9A SBC A,D
9B SBC A,E
9C SBC A,H
9D SBC A,L
9E SBC A,(HL)
9F SBC A,A
Opcode Mnemonic
A0 AND B
A1 AND C
A2 AND D
A3 AND E
A4 AND H
A5 AND L
A6 AND (HL)
A7 AND A
Opcode Mnemonic
A8 XOR B
A9 XOR C
AA XOR D
AB XOR E
AC XOR H
AD XOR L
AE XOR (HL)
AF XOR A
Opcode Mnemonic
B0 OR B
B1 OR C
B2 OR D
B3 OR E
B4 OR H
B5 OR L
B6 OR (HL)
B7 OR A
Opcode Mnemonic
B8 CP B
B9 CP C
BA CP D
BB CP E
BC CP H
BD CP L
BE CP (HL)
BF CP A
Opcode Mnemonic
C0 RET NZ
C1 POP BC
C2 xx xx JP NZ,nn
C3 xx xx JP nn
C4 xx xx CALL NZ,nn
C5 PUSH BC
C6 xx ADD A,n
C7 RST #0
Opcode Mnemonic
C8 RET Z
C9 RET
CA xx xx JP Z,nn
CB Instruction prefix
CC xx xx CALL Z,nn
CD xx xx CALL nn
CE xx ADC A,n
CF RST #8
Opcode Mnemonic
D0 RET NC
D1 POP DE
D2 xx xx JP NC,nn
D3 xx OUT (n),A
D4 xx xx CALL NC,nn
D5 PUSH DE
D6 xx SUB n
D7 RST #10
Opcode Mnemonic
D8 RET C
D9 EXX
DA xx xx JP C,nn
DB xx IN A,(n)
DC xx xx CALL C,nn
DD Instruction prefix
DE xx SBC A,n
DF RST #18
Opcode Mnemonic
E0 RET PO
E1 POP HL
E2 xx xx JP PO,nn
E3 EX (SP),HL
E4 xx xx CALL PO,nn
E5 PUSH HL
E6 xx AND n
E7 RST #20
Opcode Mnemonic
E8 RET PE
E9 JP (HL)
EA xx xx JP PE,nn
EB EX DE,HL
EC xx xx CALL PE,nn
ED Instruction prefix
EE xx XOR n
EF RST #28
Opcode Mnemonic
F0 RET P
F1 POP AF
F2 xx xx JP P,nn
F3 DI
F4 xx xx CALL P,nn
F5 PUSH AF
F6 xx OR n
F7 RST #30
Opcode Mnemonic
F8 RET M
F9 LD SP,HL
FA xx xx JP M,nn
FB EI
FC xx xx CALL M,nn
FD Instruction prefix
FE xx CP n
FF RST #38

CB-prefixed opcodes

Opcode Mnemonic
00 RLC B
01 RLC C
02 RLC D
03 RLC E
04 RLC H
05 RLC L
06 RLC (HL)
07 RLC A
Opcode Mnemonic
08 RRC B
09 RRC C
0A RRC D
0B RRC E
0C RRC H
0D RRC L
0E RRC (HL)
0F RRC A
Opcode Mnemonic
10 RL B
11 RL C
12 RL D
13 RL E
14 RL H
15 RL L
16 RL (HL)
17 RL A
Opcode Mnemonic
18 RR B
19 RR C
1A RR D
1B RR E
1C RR H
1D RR L
1E RR (HL)
1F RR A
Opcode Mnemonic
20 SLA B
21 SLA C
22 SLA D
23 SLA E
24 SLA H
25 SLA L
26 SLA (HL)
27 SLA A
Opcode Mnemonic
28 SRA B
29 SRA C
2A SRA D
2B SRA E
2C SRA H
2D SRA L
2E SRA (HL)
2F SRA A
Opcode Mnemonic
30 SLL B
31 SLL C
32 SLL D
33 SLL E
34 SLL H
35 SLL L
36 SLL (HL)
37 SLL A
Opcode Mnemonic
38 SRL B
39 SRL C
3A SRL D
3B SRL E
3C SRL H
3D SRL L
3E SRL (HL)
3F SRL A
Opcode Mnemonic
40 BIT 0,B
41 BIT 0,C
42 BIT 0,D
43 BIT 0,E
44 BIT 0,H
45 BIT 0,L
46 BIT 0,(HL)
47 BIT 0,A
Opcode Mnemonic
48 BIT 1,B
49 BIT 1,C
4A BIT 1,D
4B BIT 1,E
4C BIT 1,H
4D BIT 1,L
4E BIT 1,(HL)
4F BIT 1,A
Opcode Mnemonic
50 BIT 2,B
51 BIT 2,C
52 BIT 2,D
53 BIT 2,E
54 BIT 2,H
55 BIT 2,L
56 BIT 2,(HL)
57 BIT 2,A
Opcode Mnemonic
58 BIT 3,B
59 BIT 3,C
5A BIT 3,D
5B BIT 3,E
5C BIT 3,H
5D BIT 3,L
5E BIT 3,(HL)
5F BIT 3,A
Opcode Mnemonic
60 BIT 4,B
61 BIT 4,C
62 BIT 4,D
63 BIT 4,E
64 BIT 4,H
65 BIT 4,L
66 BIT 4,(HL)
67 BIT 4,A
Opcode Mnemonic
68 BIT 5,B
69 BIT 5,C
6A BIT 5,D
6B BIT 5,E
6C BIT 5,H
6D BIT 5,L
6E BIT 5,(HL)
6F BIT 5,A
Opcode Mnemonic
70 BIT 6,B
71 BIT 6,C
72 BIT 6,D
73 BIT 6,E
74 BIT 6,H
75 BIT 6,L
76 BIT 6,(HL)
77 BIT 6,A
Opcode Mnemonic
78 BIT 7,B
79 BIT 7,C
7A BIT 7,D
7B BIT 7,E
7C BIT 7,H
7D BIT 7,L
7E BIT 7,(HL)
7F BIT 7,A
Opcode Mnemonic
80 RES 0,B
81 RES 0,C
82 RES 0,D
83 RES 0,E
84 RES 0,H
85 RES 0,L
86 RES 0,(HL)
87 RES 0,A
Opcode Mnemonic
88 RES 1,B
89 RES 1,C
8A RES 1,D
8B RES 1,E
8C RES 1,H
8D RES 1,L
8E RES 1,(HL)
8F RES 1,A
Opcode Mnemonic
90 RES 2,B
91 RES 2,C
92 RES 2,D
93 RES 2,E
94 RES 2,H
95 RES 2,L
96 RES 2,(HL)
97 RES 2,A
Opcode Mnemonic
98 RES 3,B
99 RES 3,C
9A RES 3,D
9B RES 3,E
9C RES 3,H
9D RES 3,L
9E RES 3,(HL)
9F RES 3,A
Opcode Mnemonic
A0 RES 4,B
A1 RES 4,C
A2 RES 4,D
A3 RES 4,E
A4 RES 4,H
A5 RES 4,L
A6 RES 4,(HL)
A7 RES 4,A
Opcode Mnemonic
A8 RES 5,B
A9 RES 5,C
AA RES 5,D
AB RES 5,E
AC RES 5,H
AD RES 5,L
AE RES 5,(HL)
AF RES 5,A
Opcode Mnemonic
B0 RES 6,B
B1 RES 6,C
B2 RES 6,D
B3 RES 6,E
B4 RES 6,H
B5 RES 6,L
B6 RES 6,(HL)
B7 RES 6,A
Opcode Mnemonic
B8 RES 7,B
B9 RES 7,C
BA RES 7,D
BB RES 7,E
BC RES 7,H
BD RES 7,L
BE RES 7,(HL)
BF RES 7,A
Opcode Mnemonic
C0 SET 0,B
C1 SET 0,C
C2 SET 0,D
C3 SET 0,E
C4 SET 0,H
C5 SET 0,L
C6 SET 0,(HL)
C7 SET 0,A
Opcode Mnemonic
C8 SET 1,B
C9 SET 1,C
CA SET 1,D
CB SET 1,E
CC SET 1,H
CD SET 1,L
CE SET 1,(HL)
CF SET 1,A
Opcode Mnemonic
D0 SET 2,B
D1 SET 2,C
D2 SET 2,D
D3 SET 2,E
D4 SET 2,H
D5 SET 2,L
D6 SET 2,(HL)
D7 SET 2,A
Opcode Mnemonic
D8 SET 3,B
D9 SET 3,C
DA SET 3,D
DB SET 3,E
DC SET 3,H
DD SET 3,L
DE SET 3,(HL)
DF SET 3,A
Opcode Mnemonic
E0 SET 4,B
E1 SET 4,C
E2 SET 4,D
E3 SET 4,E
E4 SET 4,H
E5 SET 4,L
E6 SET 4,(HL)
E7 SET 4,A
Opcode Mnemonic
E8 SET 5,B
E9 SET 5,C
EA SET 5,D
EB SET 5,E
EC SET 5,H
ED SET 5,L
EE SET 5,(HL)
EF SET 5,A
Opcode Mnemonic
F0 SET 6,B
F1 SET 6,C
F2 SET 6,D
F3 SET 6,E
F4 SET 6,H
F5 SET 6,L
F6 SET 6,(HL)
F7 SET 6,A
Opcode Mnemonic
F8 SET 7,B
F9 SET 7,C
FA SET 7,D
FB SET 7,E
FC SET 7,H
FD SET 7,L
FE SET 7,(HL)
FF SET 7,A

ED-prefixed opcodes

The opcodes that are not mentioned in the following table are EDNOP (ED-prefixed NOP instruction). Thay have no effect but take 8 cycles and increment the register R two times. EDED, EDDD, EDFD and EDCB are also EDNOP instructions.

Opcode Mnemonic
40 IN B,(C)
41 OUT (C),B
42 SBC HL,BC
43 xx xx LD (nn),BC
44 NEG
45 RETN
46 IM 0
47 LD I,A
Opcode Mnemonic
48 IN C,(C)
49 OUT (C),C
4A ADC HL,BC
4B xx xx LD BC,(nn)
4C NEG
4D RETI
4E IM 0
4F LD R,A
Opcode Mnemonic
50 IN D,(C)
51 OUT (C),D
52 SBC HL,DE
53 xx xx LD (nn),DE
54 NEG
55 RETN
56 IM 1
57 LD A,I
Opcode Mnemonic
58 IN E,(C)
59 OUT (C),E
5A ADC HL,DE
5B xx xx LD DE,(nn)
5C NEG
5D RETN
5E IM 2
5F LD A,R
Opcode Mnemonic
60 IN H,(C)
61 OUT (C),H
62 SBC HL,HL
63 xx xx LD (nn),HL
64 NEG
65 RETN
66 IM 0
67 RRD
Opcode Mnemonic
68 IN L,(C)
69 OUT (C),L
6A ADC HL,HL
6B xx xx LD HL,(nn)
6C NEG
6D RETN
6E IM 0
6F RLD
Opcode Mnemonic
70 IN F,(C)
71 OUT (C),0
72 SBC HL,SP
73 xx xx LD (nn),SP
74 NEG
75 RETN
76 IM 1
77 EDNOP
Opcode Mnemonic
78 IN A,(C)
79 OUT (C),A
7A ADC HL,SP
7B xx xx LD SP,(nn)
7C NEG
7D RETN
7E IM 2
7F EDNOP
Opcode Mnemonic
A0 LDI
A1 CPI
A2 INI
A3 OUTI
Opcode Mnemonic
A8 LDD
A9 CPD
AA IND
AB OUTD
Opcode Mnemonic
B0 LDIR
B1 CPIR
B2 INIR
B3 OTIR
Opcode Mnemonic
B8 LDDR
B9 CPDR
BA INDR
BB OTDR

Notes:

  • The opcode ED70 reads the port indicated by the register C without keeping the result, but it modifies the register F
  • The opcode ED71 is used in many PSG players/drivers, as it's very useful for the PSG access, which sits behind the PPI. But beware, on a CMOS Z80 this opcode behaves differently. It corresponds to the instruction OUT (C),#FF instead Source
  • The opcode EDFF is used by Winape (and other emulators) to break into the debugger (a 'break opcode') Source

DD or FD-prefixed opcodes

If an opcode is prefixed by DD, the instruction is changed as follows:

  • HL is replaced by IX
  • H is replaced by IXH
  • L is replaced by IXL
  • (HL) is replaced by (IX+d)

Same for the FD prefix but with IY instead of IX.

There are 3 exceptions:

  • In the instruction EX DE,HL, HL will not be replaced with IX or IY. The EXX instruction is not affected either.
  • If (HL) and L or H are used in the same instruction, L and H are not replaced with IXL or IXH. For instance LD L,(IX+d) stores the content of (IX+d) into L, not IXL.
  • DD, ED or FD prefixes cancel the effects of immediately preceding DD or FD prefixes (those become NONI: No Op No Interrupt). In other words, ED-prefixed opcodes cannot be altered by DD or FD prefixes.

DDCB or FDCB-prefixed opcodes

When a DD or FD prefix is followed by a CB byte, the CB acts as a second prefix. A mandatory displacement byte comes next, and then the actual opcode.

If the instruction produces output other than in the flags (i.e. all except BIT), then the result gets placed both into (IX+d) or (IY+d) and into the register one would normally expect to be altered.

DDCB and FDCB-prefixed instructions only increment the R register twice. Source


Optimization

  • RLA, RRA, RLCA, RRCA are essentially optimized versions, one byte smaller and one M-cycle faster, of RL A, RR A, RLC A, RRC A.
  • ADD A,A is one byte smaller and one M-cycle faster than SLA A.
  • Similarly, ADD HL,HL is 3 bytes smaller and one M-cycle faster than SLA L; RL H.
  • DJNZ loop is one byte smaller and is as fast as DEC B; JR nz,loop on CPC.
  • For a smaller conditional RST #38, use JR cc,-1. This will cause a conditional jump to the displacement byte (#FF) which is the RST #38 opcode.
  • To quickly invert all bits of A, CPL is one byte shorter and one M-cycle faster than XOR #FF.
  • To set A to zero, XOR A is one byte smaller and one M-cycle faster than LD A,0.
  • To check if A is zero, AND A or OR A are one byte smaller and one M-cycle faster than CP 0.
  • An unrolled LDI loop is faster than LDIR. The same applies to other Z80 block instructions.
  • If tables are aligned to a 256-byte boundary, the contents can be accessed by placing the index in a register such as L and the table address in H. This is faster than loading the full unaligned 16-bit address and adding a 16-bit index to it, and makes accessing tables with a size of 256 bytes or less very convenient.


Oddities

  • RETI and RETN are identical instructions Source. The only reason for RETI is so that some other hardware can detect the specific case of returning from the interrupt, by detecting the RETI opcode on the data bus.
  • EI has a 1-instruction delay. It is necessary for doing EI/RETI without any danger of nested interrupt routines.
  • At the end of an NMI service routine, the earliest moment a maskable interrupt will be triggered is at the end of the instruction following RETN. Source
  • RST instructions are just a CALL instruction to a fixed address baked in the instruction itself.
  • Unlike the conditional JP, CALL, RET instructions which have access to all conditions, JR is limited to NZ, Z, NC, C conditions.
  • Despite what the syntax of the instructions JP (HL/IX/IY) suggests, PC will be loaded with the contents of the register itself, not the indexed value. Those instructions should be understood as JP HL/IX/IY.
  • The instructions LD A,A, LD B,B, LD C,C, LD D,D, LD E,E, LD H,H and LD L,L are useless. Their existence is just a side effect of how instructions are encoded as opcodes in the CPU.
  • The instructions LD (nn),HL and LD HL,(nn) exist both as standard opcodes and ED-prefixed opcodes.
  • The 16-bit instructions ADD HL,ss, ADC HL,ss and SBC HL,ss exist but not the instruction SUB HL,ss.
  • While the syntax of the 8-bit ADD, ADC and SBC instructions all explicitly mention the A register, the SUB instruction does not mention it. On the Zilog eZ80, the SUB instruction explicitly mention the A register.
  • The Z80 has a lot of 8-bit registers but it can only really do arithmetic on one of them, A.
  • The IN r,(C) instruction updates flags but IN A,(n) does not.
  • IN r,(C) and OUT (C),r instructions syntax is misleading as these instructions actually use the full 16-bit port address contained in BC. On the Zilog eZ80, these instructions are correctly named IN, r,(BC) and OUT (BC),r.
  • The Amstrad engineers chose to use the high byte of the address (register B) for chip selection instead of the low byte (register C) in I/O operations. As a result, OTIR / OTDR / INIR / INDR instructions cannot be used on Amstrad CPC for transferring or reading a sequence of values on a port, as these instructions use the B register as a counter.
  • INI/IND/INIR/INDR decrease B after storing the byte from the hardware port into memory. And OUTI/OUTD/OTIR/OTDR decrease B before sending the memory byte to the hardware port. Source
  • All PUSH and POP instructions utilize a 16-bit operand and the high-order byte is always pushed first and popped last. PUSH HL is PUSH H then L. POP HL is POP L then H.
  • When an LDxR / CPxR / INxR / OTxR instruction is interrupted, the interrupt handler sees some flags in a different state. Source
  • LD A,I and LD A,R normally copy the state of IFF2 to the Parity flag. NMOS Z80 suffers a problem whereby LD A,I and LD A,R record the state of IFF2 after it has been reset if an interrupt is delivered during that instruction. Source
  • Although not mentioned in Zilog documentation, the Z80 CPU supports two types of reset: normal and special. A normal reset disables the maskable interrupt, selects interrupt mode 0, zeroes registers I & R and zeroes the program counter (PC). A special reset zeroes PC only. Furthermore, a hardware bug was discovered when the special reset occurs after a HALT instruction. Source
  • Almost all Z80 inputs are sampled on a rising clock, but the /WAIT signal is sampled on a falling clock. Source
  • The 6502’s Decimal (BCD) mode automatically adjusts ADC and SBC results, while the Z80 requires a DAA instruction after each BCD addition and subtraction.
  • The 6502 uses only one addressing mode per instruction, while the Z80 can combine two different addressing modes within a single instruction.
  • The 6502 post-decrements on PHA and pre-increments on PLA, while the Z80 pre-decrements on PUSH and post-increments on POP.
  • The 6502 saves flags automatically during interrupts; while the Z80 requires PUSH AF and POP AF.


Block Diagrams

Z80 Block Diagram.gif


Z80-top-level-partitions.jpg

See: How the Z80's registers are implemented The 16-bit increment/decrement circuit The 4-bit ALU


Timing Diagrams

  • Basic CPU Timing

  • Opcode Fetch

  • Memory Read or Write

  • Interrupt Request

  • NMI Request

  • Input or Output

  • Bus Request

  • HALT Exit


The Decode ROM (PLA)

The Z80 is based around a more complicated structure than the 6502. Here the instruction is sent through a (rather) simple decoder. The decoder is built from a PLA. Simple because 8080/Z80 code offer fewer variants (i.e. addressing modes) and is quite regular compared with a 6502. The decoder creates multiple lines for each instruction or instruction group, which are fed into the second stage.

Two counters are set up in parallel. One counting the Memory (or Machine) states (M1..M5), the other Time states (T1..T5) within (note1). With a new instruction the M counter gets reset to 1, with each M state the T counter gets reset.

The second stage of instruction decode is something that is much like another PLA, but built out of single gates (note2). The gates are set up much like a grid with the timing signals (M1..M5 & T1..T5) as horizontal input and the PLA output (instructions/instruction groups) as vertical input. The gate is built along the vertical line and combining its signal with one or more timing signals using AND/NOR logic (note3). The output of these gates are fed into the discrete logic of the execution units. Source

  • note1: this internal structure is also the reason for this otherwise unusual notation used throughout all Z80 documentation.
  • note2: The structure is quite similar to a gate array - except that only needed inputs/functions are cast into silicon.
  • note3: CMOS offers the feature to build rather complex gates with multiple inputs in a simple way - to some extend this is maybe the most unique feature about the Z80 design.

See: ARM1, Z80, 6502 instruction sequencing compared Z80 instruction decode PLA table Script processing the PLA table


CPU Pinout

Z80 Pins.png

  • RFSH = outputs a signal to allow for memory to be refreshed
  • M1 = Z80 is fetching next instruction from memory
  • RESET = used to reset the Z80
  • BUSRQ = Bus Request (used by external devices to request control)
  • WAIT = makes the the Z80 wait during a read or write operation
  • BUSACK = Bus Acknowledge – signals when Z80 is ready to hand over control
  • WR = signals a memory or I/O write operation
  • RD = signals a memory or I/O read operation
  • INT = hardware interrupt occurred
  • NMI = Non Maskable Interrupt (higher priority than the INT)
  • HALT = Z80 is in a halted state
  • MREQ = Z80 wants to access memory
  • IORQ = Z80 wants to access an I/O port

See: Why Z80's data pins are scrambled


Chip Variants

The GBZ80 (Sharp SM83) that powers the original Nintendo GameBoy is an in-between the Intel 8080 and Z80. Source Game Boy CPU Manual Game Boy complete technical reference Reverse engineering the Game Boy hardware The Ultimate Game Boy Talk Emudev (gb-si) Game Boy test roms

Fun fact: Way more GBZ80 cores were produced for Gameboy hardware (118 million Gameboys and 81 million GBA) than all the Z80 chips produced for home computers and game consoles.

The Sega Mega Drive, Master System and Game Gear use a standard Z80 CPU. Genesis sound software manual Master System reference manual Game Gear reference manual

The KC Compact uses the U880, which is an unlicensed clone of the Z80 manufactured by MME. It was the most widely used microprocessor in the German Democratic Republic. Source

The КМ1582ВМ-0100 is a Soviet clone of the Z80. It is used in the Aleste 520EX clone of the Amstrad CPC computer.

The ASCII R800 that powers the MSX TurboR is a seriously beefed up version of the Z80:

  • The ALU of the R800 is 16-bit instead of 4-bit for the Z80. This change allows instructions that were being executed in 4 cycles to be done in 1 cycle.
  • The instruction set of the R800 is almost identical to the Z80. Only 2 instructions have been added: MULUB and MULUW. And many of the undocumented instructions of the Z80 were made official.

Zilog itself offers the eZ80 processor, a binary-compatible upgrade of the Z80, which runs at up to 50MHz but performs like a 150MHz Z80 due to being 3 times faster at the same clock speed.


Manuals


Weblinks

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