Difference between revisions of "CRTC"

Latest revision as of 17:53, 20 December 2024

The 6845 CRTC (Cathode Ray Tube Controller) chip was created by Motorola in 1977. It works with the Gate Array to generate the video signal on the Amstrad CPC.

This chip is also used in the BBC Micro, Sharp X1, MicroBee, Commodore PET and the early graphics cards (MDA, Hercules, CGA, Plantronics Colorplus) for IBM PC. And it is found in some MSX1 expansions, providing an 80-column text mode.

NOTES:

• This document describes the functionality in terms of the CPC with its separate CRTC and Gate-Array. The Plus has both integrated into the same IC, but could be considered to have two functional blocks, one for CRTC and one for Gate-Array. In this document the term 'Gate-Array' is used, but this also applies to the ASIC.
• Much information has been drawn from the CRTC Compendium documentation, condensed and rearranged for clarity. For details, timing diagrams, code examples, coding tips, and more, refer to that documentation.

Overview

The 6845 Cathode Ray Tube Controller (CRTC) is a programmable IC used to generate video displays. This IC is used in a variety of computers including the Amstrad CPC, Amstrad Plus and KC Compact.

The CRTC is a simple chip. It is made up of counters and equality operators, tied by simple logic. All the complexity stems from its multiple independent implementations with their subtle differences.

The CRTC was a common part available from many different manufacturers. During the life of the CPC, Amstrad sourced the CRTC from various manufacturers.

All ICs used were based on the same design but have a different implementation. As a result they do not operate identically in all situations. This document highlights these differences.

This table lists the known ICs used, with their part number, manufacturer and type number.

NOTES

1. The CRTC functionality is integrated into the CPC+ ASIC. This type exists only in the 464 Plus, 6128 Plus and GX4000.

2. This type exists in "cost-down" CPC464 and CPC6128 systems. In the "cost-down" the CRTC functionality is integrated into a single ASIC IC. This ASIC is often refered to as the "Pre-ASIC" because it preceeded the CPC+ ASIC. The CRTC functionality of the Pre-ASIC is almost identical to the CRTC within the ASIC.

3. In the Amstrad community each 6845 implementation has been assigned a type number. This type identifies a group of implementations which operate in exactly the same way. The type number system was originally used by demo programmers.

It is possible to detect the 6845 present using software methods, and this is done to:

• warn that the software was not designed for the detected 6845 and may function incorrectly
• to adapt the software so that it will run with the detected 6845
• In most cases, the type of the detected 6845 is reported

Programming

The 6845 is selected when bit 14 of the I/O port address is set to "0". Bit 9 and 8 of the I/O port address define the function to access. The remaining bits can be any value, but it is adviseable to set these to "1" to avoid conflict with other devices in the system.

The recommended I/O port addresses are:

The CRTC is not connected to the CPU's RD and WR pins, so it cannot detect the bus's I/O direction. Therefore, executing an IN instruction to the select or write functions causes the CRTC to write the unpredictable data provided by the high-impedance bus to its registers.

Z80 I/O access timings

The clock provided to the CRTC by the ASIC/Pre-ASIC is phase-shifted compared to the one provided by the Gate Array.

Video Memory Address (VMA)

The VMA of the Gate Array is constructed from the CRTC MA and RA signals:

CRTC generates the address, Gate Array reads the data and converts it to pixels based on its current graphics mode and palette.

CRTC pins RA3, RA4, MA10, MA11 are not connected on CPC.

Overscan bits

It's possible to use 32KB screen size (used for overscan) by setting bits 11 and 10 of Register 12 both to 1. Bits MA11 and MA10 of the address generated by the CRTC are not written on the address bus to access video memory; settings both bits to 1 is the only way to cause a carry to bit MA12 when address pass over the end of current video page to change the memory address to the next video page.

Hardware scrolling

The start address can be manipulated to achieve horizontal and/or vertical hardware scrolling:

• To move right: start_address = start_address + 1
• To move left: start_address = start_address - 1
• To move down: start_address = start_address + R1
• To move up: start_address = start_address - R1

However, it is a position in word (16 bits), not in byte. So, the screen will move two bytes at a time horizontally. Also, the precision will be one CRTC character vertically.

The first game that used R12/R13 for both horizontal and vertical hardware scrolling is Roland on the Ropes, released in 1984.

To achieve smoother hardware scrolling, other tricks are required in complement to R12/R13. Usually, R3 is used for smooth horizontal scroll and R5 for smooth vertical scroll.

A good example of smooth hardware multidirectional scrolling game on CPC is Super Cauldron, released in 1993.

Split screen

While there is usually 1 CRTC frame per screen frame, the screen frame can be divided into multiple CRTC frames of varying proportions.

Some rules of thumb Source:

• changes to the screen address have to be done anywhere in the previous split
• changes to the height of the split have to be done inside the current split (after it has started, in the area of the size of the previous split)
• changes to screen mode and colours are happening immediately

CRTC registers and screen splitting:

• reg 0 (63) = x-screenwidth (usually always 63)
• reg 1 (50) = x-splitwidth (e.g.50)
• reg 2 (51) = x-splitstart (e.g. 51)
• reg 3 (08) = x-finestart (maybe use this for half-char scrolling)
• reg 4 (##) = y-splitheight-1 (set this inside the current split)
• reg 5 (00) = y-finestart
• reg 6 (25) = y-max visible splitpart (same like 4)
• reg 7 (##) = inside last split -> set to 0; inside first split, but after vblank -> set to 255
• reg 9 (07) = y-lines/char-1

Set this inside the previous split:

• reg12 (##) = address high (char / 256 + block * 16)
• reg13 (##) = address low (char mod 256)

Total height of all splits must be 39.

CUDISP (aka CURSOR)

CUDISP (Cursor Display) signal defines the hardware cursor.

CRTC pin CUDISP is not connected to the Gate Array, so it has no effect on a barebone CPC or Plus machine.

However, this signal is provided to the expansion port. And it is used by the PlayCity and Play2CPC expansions.

DISPTMG (aka Display Enable)

DISPTMG (Display Timing) signal defines the border. When DISPTMG is "0" the border colour is output by the Gate Array to the display.

The border has higher priority than pixels but lower priority than the black colour output when HSYNC/VSYNC are active.

While border is active, all the CRTC counters continue to increment normally and addresses continue to be generated.

The DISPTMG signal is composited from its 3 internal subcomponents: HBORDER (Horizontal), VBORDER (Vertical), SBORDER (Split) by using the NOR function. DISPTMG is "0" if at least one of its subcomponents is "1". These 3 subcomponents are all independent of each other.

HBORDER

On all CRTCs, HBORDER is disabled when HCC=0 and enabled when HCC=R1.

The exception is for CRTC2 during an HSYNC: the HCC=0 check is skipped, so HBORDER stays on.

VBORDER

On all CRTCs, VBORDER is disabled when VCC=0 and enabled when VCC=R6.

On CRTCs 0/1/2, the condition VCC=R6 is tested on every cycle.

On CRTCs 3/4, the condition VCC=R6 is tested only at each new character line start (when VLC=0 and HCC=0).

SBORDER

Split border is a technique similar to split rasters, except that it is handled by the CRTC instead of the Gate Array.

DISPTMG can be temporarily forced to 0 by using R8 (DISPTMG Skew) on CRTCs 0/3/4, or by setting R6=0 on CRTC 1.

It is not possible to force DISPTMG on CRTC 2.

Border bytes

Despite their 1MHz clock speed, CRTCs 0/2 have been observed to change state at a rate equivalent to 2MHz chips by responding to both the rising and falling edges of each clock cycle.

Interline border

On CRTCs 0/2, R1>R0 generates one byte (0.5µs) of border at the end of the raster line. On CRTCs 1/3/4, it does not.

If border skew is used, the border byte will skew and change into a full character-width border instead.

Border conflict

If R1=0 and HCC=0, we expect HBORDER to activate as HCC=R1 and we also expect HBORDER to deactivate as HCC=0. In this situation, all CRTCs activate HBORDER.

If R6=0 and VCC=0, we expect VBORDER to activate as VCC=R6 and we also expect VBORDER to deactivate as VCC=0. In this situation, all CRTCs activate VBORDER. On CRTC 1, even SBORDER is activated. But on CRTCs 0/2, the first raster line shows an alternation of bytes of VBORDER and displayable characters.

To see the border bytes with your own eyes, type this BASIC line after reset:

BORDER 6:OUT &BC00,6:OUT &BD00,0

HSYNC

The HSYNC signal from the CRTC is not directly connected to the display. It is passed to the Gate Array for further modification. See its wiki page.

While HSYNC is active, all the CRTC counters continue to increment normally and addresses continue to be generated.

On all CRTCs, while an HSYNC is ongoing, the condition HCC=R2 is ignored. So we cannot trigger a new HSYNC during an HSYNC.

Contiguous HSYNCs

On CRTC 0, two HSYNCs cannot be contiguous. They are always separated by at least 1 CRTC character. What happens is that when HSC=R3 and HCC=R2, the condition HSC=R3 takes precedence over the condition HCC=R2 and HSYNC is stopped.

On CRTCs 1/2/3/4, HSYNCs can be contiguous.

Signal delay

On all CRTCs, there is a 1µs delay in display between when the CRTC provides a video pointer, and when the Gate Array displays the corresponding 16-bit character.

But on CRTCs 0/1/2, there is no delay for HSYNC. On CRTCs 3/4, the Amstrad engineers fixed the issue by adding a 1µs delay for the HSYNC signal to match the display signal.

So now we have a bigger issue: on CRTCs 3/4, HSYNC occurs 1µs later than on CRTCs 0/1/2. Interrupts being dependent on HSYNC, this is a serious compatibility issue for time-sensitive code. It also explains why the CTM monitor has to be calibrated differently on CRTCs 3/4. Fortunately, the issue is easy to fix, by adjusting the HSYNC width with CRTC register 3.

Discolouration effect

On CRT monitors from other brands, a colour calibration can happen just after the C-HSYNC pulse.

So even when a fully valid C-HSYNC pulse of 4µs is emitted, an HSYNC shorter than usual combined with a coloured border can induce a discolouration effect on those monitors.

Screen wobbling and Fine horizontal hardware scroll

These effects use invalid HSYNC signals, which are poorly supported by modern displays. However, these effects were used in commercial-era CPC games, so it's fine if you choose to use them.

When R2 increases by 1, the screen is shifted to the left by 16 mode2 pixels.

When R2 decreases by 1, the screen is shifted to the right by 16 mode2 pixels.

When R3l increases by 1 (and if <6), the screen is shifted to the left by 8 mode2 pixels.

When R3l decreases by 1 (and if >2), the screen is shifted to the right by 8 mode2 pixels.

The shift is not instantaneous but follows a logarithmic attenuation across several raster lines. This property can be used to get even finer horizontal control by modifying R2/R3 on each raster line.

Longshot has demonstrated horizontal hardware scroll with one-pixel precision in mode1 on all CRTCs. However, because you have to synchronize with each line, it takes a lot of CPU time if it's done in fullscreen (272 lines).

VSYNC

The VSYNC signal from the CRTC is not directly connected to the display. It is passed to the Gate Array for further modification. See its wiki page.

While VSYNC is active, all the CRTC counters continue to increment normally and addresses continue to be generated.

On all CRTCs, while a VSYNC is ongoing, the condition VCC=R7 is ignored. So we cannot trigger a new VSYNC during a VSYNC.

On CRTCs 0/1/2, the sole condition to trigger a VSYNC is that VCC=R7. While on CRTCs 3/4, it is necessary to have VCC=R7 and HCC=0 and VLC=0 to trigger a VSYNC.

Blocked VSYNC

On CRTC 0, if R7 is modified with the value of VCC when HCC<2, we are in blocked VSYNC. Then, the VSYNC can no longer occur on VCC=R7 until an unblocking condition is produced (VCC or R7 update). Source: §16.4 "Conditions to consider" of the CRTC Compendium

Ghost VSYNC

On CRTC 2, if a VSYNC is triggered during an HSYNC, the CRTC produces a ghost VSYNC. The CRTC then counts the lines as if a VSYNC were taking place by preventing a new VSYNC from occurring, but without the VSYNC pin being enabled.

PPI VSYNC

The VSYNC pin of the CRTC is directly connected to bit0 of port B of the PPI. There is no delay involved.

On Amstrad CPC (not Plus!), it is also possible to reverse the direction of PPI port B to output a "fake" VSYNC signal directly from the PPI to the Gate Array.

As an exception, the Ghost VSYNC of CRTC 2 overpowers the Fake VSYNC.

Subpixel vertical hardware scroll

By tuning very precisely when the VSYNC signal is sent to the monitor, Longshot has demonstrated vertical hardware scroll with a precision of 1/128th of a pixel. Furthermore, subpixel vertical scrolling consumes very little CPU.

Mid-VSYNC

On all CRTCs, in both interlace modes, a mid-VSYNC is generated when VCC=R7 on the even field. The VSYNC pulse starts in the middle of the raster line, at HCC=R0/2.

As an exception, on CRTCs 3/4, if R7=0 then mid-VSYNC will instead occur on the odd field. Source: §19.7 "Mid-VSYNC" of the CRTC Compendium.

Interlace modes

Note: A lot of details about the CRTC interlace implementations are missing in this article. Consider it as an introduction to the topic.

For a CRTC character line with n raster lines, R9 must be set to n-1 on all CRTCs, regardless of the interlace settings. The exception is for CRTCs 0/3/4 in IVM mode, where R9 must be set to n-2.

Interlace sync mode (ISM)

In this mode, the same information is painted in both fields to enhance readability. Reprogramming the CRTC is not necessary.

Interlace sync and video mode (IVM)

In this mode, alternating lines are displayed in the even and odd field to double the resolution.

On the even field, the CRTC displays the lines for which VLC is even. On the odd field, the CRTC displays the lines for which VLC is odd.

It is necessary to reprogram the CRTC as if we were building a frame of 624 lines.

CRTC 2 is the exception: R4, R5, R6, R7 do not need to be reprogrammed as it considers each character line to be a double character line.

Interlace adjustment line

On all CRTCs, in both interlace modes, an additional line (the 625th line) is added automatically by the CRTC at the end of the even field. This line is added after the lines of the vertical adjustment mode.

CRTC registers

The Internal registers of the 6845 are: