Difference between revisions of "CRTC"

Latest revision as of 18:29, 19 November 2024

The 6845 CRTC (Cathode Ray Tube Controller) chip was created by Motorola in 1977. It works with the Gate Array to generate the video signal on the Amstrad CPC.

This chip is also used in the BBC Micro, Sharp X1, MicroBee, Commodore PET and the early graphics cards (MDA, Hercules, CGA, Plantronics Colorplus) for IBM PC. And it is found in some MSX1 expansions, providing an 80-column text mode.

NOTES:

• This document describes the functionality in terms of the CPC with its separate CRTC and Gate-Array. The Plus has both integrated into the same IC, but could be considered to have two functional blocks, one for CRTC and one for Gate-Array. In this document the term 'Gate-Array' is used, but this also applies to the ASIC.
• Much information has been drawn from the CRTC Compendium documentation, condensed and rearranged for clarity. For details, timing diagrams, code examples, coding tips, and more, refer to that documentation.

Overview

The 6845 Cathode Ray Tube Controller (CRTC) is a programmable IC used to generate video displays. This IC is used in a variety of computers including the Amstrad CPC, Amstrad CPC+ and KC Compact.

The CRTC is a simple chip. It is made up of counters and equality operators, tied by simple logic. All the complexity stems from its multiple independent implementations with their subtle differences.

The CRTC was a common part available from many different manufacturers. During the life of the CPC, Amstrad sourced the CRTC from various manufacturers.

All ICs used were based on the same design but have a different implementation. As a result they do not operate identically in all situations. This document highlights these differences.

This table lists the known ICs used, with their part number, manufacturer and type number.

NOTES

1. The CRTC functionality is integrated into the CPC+ ASIC. This type exists only in the CPC464+,CPC6128+ and GX4000.

2. This type exists in "cost-down" CPC464 and CPC6128 systems. In the "cost-down" the CRTC functionality is integrated into a single ASIC IC. This ASIC is often refered to as the "Pre-ASIC" because it preceeded the CPC+ ASIC. The CRTC functionality of the Pre-ASIC is almost identical to the CRTC within the ASIC.

3. In the Amstrad community each 6845 implementation has been assigned a type number. This type identifies a group of implementations which operate in exactly the same way. The type number system was originally used by demo programmers.

It is possible to detect the 6845 present using software methods, and this is done to:

• warn that the software was not designed for the detected 6845 and may function incorrectly
• to adapt the software so that it will run with the detected 6845
• In most cases, the type of the detected 6845 is reported

Z80 I/O access timings

The clock provided to the CRTC by the ASIC/Pre-ASIC is phase-shifted compared to the one provided by the Gate Array.

Programming

The 6845 is selected when bit 14 of the I/O port address is set to "0". Bit 9 and 8 of the I/O port address define the function to access. The remaining bits can be any value, but it is adviseable to set these to "1" to avoid conflict with other devices in the system.

The recommended I/O port addresses are:

The CRTC is not connected to the CPU's RD and WR pins, so it cannot detect the bus's I/O direction. Therefore, executing an IN instruction to the select or write functions causes the CRTC to write the unpredictable data provided by the high-impedance bus to its registers.

Video Memory Address (VMA)

The VMA of the Gate Array is constructed from the CRTC MA and RA signals:

CRTC generates the address, Gate Array reads the data and converts it to pixels based on its current graphics mode and palette.

CRTC pins RA3, RA4, MA10, MA11 are not connected on CPC.

Overscan bits

It's possible to use 32KB screen size (used for overscan) by setting bits 11 and 10 of Register 12 both to 1. Bits MA11 and MA10 of the address generated by the CRTC are not written on the address bus to access video memory; settings both bits to 1 is the only way to cause a carry to bit MA12 when address pass over the end of current video page to change the memory address to the next video page.

 .------- REG 12 --------.   .------- REG 13 --------.
 |                       |   |                       |
  15 14 13 12 11 10 09 08     07 06 05 04 03 02 01 00
 .--.--.--.--.--.--.--.--.   .--.--.--.--.--.--.--.--.
 |X |X |  |  |  |  |  |  |   |  |  |  |  |  |  |  |  |
 '--'--'--'--'--'--'--'--'   '--'--'--'--'--'--'--'--'
       '--.--'--.--'---------------.-----------------'
          |     |                  |
          |     |                  '------> Offset for setting videoram
          |     |                           (1024 positions) Bits 0..9
          |     |                           
          |     '-------------------------> Video Buffer
          |
          '-------------------------------> Video Page

 .--.--.---------------.   .--.--.--------------.
 |13|12|   Video Page  |   |11|10| Video Buffer |
 |--|--|---------------|   |--|--|--------------|
 | 0| 0|  0000 - 3FFF  |   | 0| 0|     16KB     |
 |--|--|---------------|   |--|--|--------------|
 | 0| 1|  4000 - 7FFF  |   | 0| 1|     16KB     |
 |--|--|---------------|   |--|--|--------------|
 | 1| 0|  8000 - BFFF  |   | 1| 0|     16KB     |
 |--|--|---------------|   |--|--|--------------|
 | 1| 1|  C000 - FFFF  |   | 1| 1|     32KB     |
 '--'--'---------------'   '--'--'--------------'

Split screen

While there is usually 1 CRTC frame per screen frame, the screen frame can be divided into multiple CRTC frames of varying proportions.

Some rules of thumb Source:

• changes to the screen address have to be done anywhere in the previous split
• changes to the height of the split have to be done inside the current split (after it has started, in the area of the size of the previous split)
• changes to screen mode and colours are happening immediately

CRTC registers and screen splitting:

• reg 0 (63) = x-screenwidth (usually always 63)
• reg 1 (50) = x-splitwidth (e.g.50)
• reg 2 (51) = x-splitstart (e.g. 51)
• reg 3 (08) = x-finestart (maybe use this for half-char scrolling)
• reg 4 (##) = y-splitheight-1 (set this inside the current split)
• reg 5 (00) = y-finestart
• reg 6 (25) = y-max visible splitpart (same like 4)
• reg 7 (##) = inside last split -> set to 0; inside first split, but after vblank -> set to 255
• reg 9 (07) = y-lines/char-1

Set this inside the previous split:

• reg12 (##) = address high (char / 256 + block * 16)
• reg13 (##) = address low (char mod 256)

Total height of all splits must be 39.

CUDISP (aka CURSOR)

CUDISP (Cursor Display) signal defines the hardware cursor.

CRTC pin CUDISP is not connected to the Gate Array, so it has no effect on a barebone CPC or Plus machine.

However, this signal is provided to the expansion port. And it is used by the PlayCity and Play2CPC expansions.

DISPTMG (aka Display Enable)

DISPTMG (Display Timing) signal defines the border. When DISPTMG is "0" the border colour is output by the Gate Array to the display.

The border has higher priority than pixels but lower priority than the black colour output when HSYNC/VSYNC are active.

While border is active, all the CRTC counters continue to increment normally and addresses continue to be generated.

The DISPTMG signal is composited from its 3 internal subcomponents: HBORDER (Horizontal), VBORDER (Vertical), SBORDER (Split) by using the NOR function. DISPTMG is "0" if at least one of its subcomponents is "1". These 3 subcomponents are all independent of each other.

HBORDER

On all CRTCs, HBORDER is disabled when HCC=0 and enabled when HCC=R1.

The exception is for CRTC2 during an HSYNC: the HCC=0 check is skipped, so HBORDER stays on.

VBORDER

On all CRTCs, VBORDER is disabled when VCC=0 and enabled when VCC=R6.

On CRTCs 0/1/2, the condition VCC=R6 is tested on every cycle.

On CRTCs 3/4, the condition VCC=R6 is tested only at each new character line start (when VLC=0 and HCC=0).

SBORDER

Split border is a technique similar to split rasters, except that it is handled by the CRTC instead of the Gate Array.

DISPTMG can be temporarily forced to 0 by using R8 (DISPTMG Skew) on CRTCs 0/3/4, or by setting R6=0 on CRTC 1.

It is not possible to force DISPTMG on CRTC 2.

Border bytes

Despite their 1MHz clock speed, CRTCs 0/2 have been observed to change state at a rate equivalent to 2MHz chips by responding to both the rising and falling edges of each clock cycle.

Interline border

On CRTCs 0/2, R1>R0 generates one byte (0.5µs) of border at the end of the raster line. On CRTCs 1/3/4, it does not.

If border skew is used, the border byte will skew and change into a full character-width border instead.

Border conflict

If R1=0 and HCC=0, we expect HBORDER to activate as HCC=R1 and we also expect HBORDER to deactivate as HCC=0. In this situation, all CRTCs activate HBORDER.

If R6=0 and VCC=0, we expect VBORDER to activate as VCC=R6 and we also expect VBORDER to deactivate as VCC=0. In this situation, all CRTCs activate VBORDER. On CRTC 1, even SBORDER is activated. But on CRTCs 0/2, the first raster line shows an alternation of bytes of VBORDER and displayable characters.

To see the border bytes with your own eyes, type this BASIC line after reset:

BORDER 6:OUT &BC00,6:OUT &BD00,0

HSYNC

The HSYNC signal from the CRTC is not directly connected to the display. It is passed to the Gate Array for further modification. See its wiki page.

While HSYNC is active, all the CRTC counters continue to increment normally and addresses continue to be generated.

On all CRTCs, while an HSYNC is ongoing, the condition HCC=R2 is ignored. So we cannot trigger a new HSYNC during an HSYNC.

Contiguous HSYNCs

On CRTC 0, two HSYNCs cannot be contiguous. They are always separated by at least 1 CRTC character. What happens is that when HSC=R3 and HCC=R2, the condition HSC=R3 takes precedence over the condition HCC=R2 and HSYNC is stopped.

On CRTCs 1/2/3/4, HSYNCs can be contiguous.

Signal delay

On all CRTCs, there is a 1µs delay in display between when the CRTC provides a video pointer, and when the Gate Array displays the corresponding 16-bit character.

But on CRTCs 0/1/2, there is no delay for HSYNC. On CRTCs 3/4, the Amstrad engineers fixed the issue by adding a 1µs delay for the HSYNC signal to match the display signal.

So now we have a bigger issue: on CRTCs 3/4, HSYNC occurs 1µs later than on CRTCs 0/1/2. Interrupts being dependent on HSYNC, this is a serious compatibility issue for time-sensitive code. It also explains why the CTM monitor has to be calibrated differently on CRTCs 3/4. Fortunately, the issue is easy to fix, by adjusting the HSYNC width with CRTC register 3.

Discolouration effect

On CRT monitors from other brands, a colour calibration can happen just after the C-HSYNC pulse.

So even when a fully valid C-HSYNC pulse of 4µs is emitted, an HSYNC shorter than usual combined with a coloured border can induce a discolouration effect on those monitors.

Screen wobbling and Fine horizontal hardware scroll

These effects use invalid HSYNC signals, which are poorly supported by modern displays. However, these effects were used in commercial-era CPC games, so it's fine if you choose to use them.

When R2 increases by 1, the screen is shifted to the left by 16 mode2 pixels.

When R2 decreases by 1, the screen is shifted to the right by 16 mode2 pixels.

When R3l increases by 1 (and if <6), the screen is shifted to the left by 8 mode2 pixels.

When R3l decreases by 1 (and if >2), the screen is shifted to the right by 8 mode2 pixels.

The shift is not instantaneous but follows a logarithmic attenuation across several raster lines. This property can be used to get even finer horizontal control by modifying R2/R3 on each raster line.

Longshot has demonstrated horizontal hardware scroll with one-pixel precision in mode1 on all CRTCs. However, because you have to synchronize with each line, it takes a lot of CPU time if it's done in fullscreen (272 lines).

VSYNC

The VSYNC signal from the CRTC is not directly connected to the display. It is passed to the Gate Array for further modification. See its wiki page.

While VSYNC is active, all the CRTC counters continue to increment normally and addresses continue to be generated.

On all CRTCs, while a VSYNC is ongoing, the condition VCC=R7 is ignored. So we cannot trigger a new VSYNC during a VSYNC.

On CRTCs 0/1/2, the sole condition to trigger a VSYNC is that VCC=R7. While on CRTCs 3/4, it is necessary to have VCC=R7 and HCC=0 and VLC=0 to trigger a VSYNC.

Blocked VSYNC

On CRTC 0, if R7 is modified with the value of VCC when HCC<2, we are in blocked VSYNC. Then, the VSYNC can no longer occur on VCC=R7 until an unblocking condition is produced (VCC or R7 update). Source: §16.4 "Conditions to consider" of the CRTC Compendium

Ghost VSYNC

On CRTC 2, if a VSYNC is triggered during an HSYNC, the CRTC produces a ghost VSYNC. The CRTC then counts the lines as if a VSYNC were taking place by preventing a new VSYNC from occurring, but without the VSYNC pin being enabled.

PPI VSYNC

The VSYNC pin of the CRTC is directly connected to bit0 of port B of the PPI. There is no delay involved.

On Amstrad CPC (not Plus!), it is also possible to reverse the direction of PPI port B to output a "fake" VSYNC signal directly from the PPI to the Gate Array.

As an exception, the Ghost VSYNC of CRTC 2 overpowers the Fake VSYNC.

Subpixel vertical hardware scroll

By tuning very precisely when the VSYNC signal is sent to the monitor, Longshot has demonstrated vertical hardware scroll with a precision of 1/128th of a pixel. Furthermore, subpixel vertical scrolling consumes very little CPU.

Mid-VSYNC

On all CRTCs, in both interlace modes, a mid-VSYNC is generated when VCC=R7 on the even field. The VSYNC pulse starts in the middle of the raster line, at HCC=R0/2.

As an exception, on CRTCs 3/4, if R7=0 then mid-VSYNC will instead occur on the odd field. Source: §19.7 "Mid-VSYNC" of the CRTC Compendium.

Interlace modes

Note: A lot of details about the CRTC interlace implementations are missing in this article. Consider it as an introduction to the topic.

For a CRTC character line with n raster lines, R9 must be set to n-1 on all CRTCs, regardless of the interlace settings. The exception is for CRTCs 0/3/4 in IVM mode, where R9 must be set to n-2.

Interlace sync mode (ISM)

In this mode, the same information is painted in both fields to enhance readability. Reprogramming the CRTC is not necessary.

Interlace sync and video mode (IVM)

In this mode, alternating lines are displayed in the even and odd field to double the resolution.

On the even field, the CRTC displays the lines for which VLC is even. On the odd field, the CRTC displays the lines for which VLC is odd.

It is necessary to reprogram the CRTC as if we were building a frame of 624 lines.

CRTC 2 is the exception: R4, R5, R6, R7 do not need to be reprogrammed as it considers each character line to be a double character line.

Interlace adjustment line

On all CRTCs, in both interlace modes, an additional line (the 625th line) is added automatically by the CRTC at the end of the even field. This line is added after the lines of the vertical adjustment mode.

CRTC registers

The Internal registers of the 6845 are:

On CRTCs 0/1/2, if a Write Only register is read from, "0" is returned. The register accessing scheme on CRTCs 3/4 makes it impossible to happen.

Register access

On all CRTCs, only the 5 least significant bits of the selected register number are considered to write to a register. The other bits are ignored.

On CRTCs 0/1/2, only the 5 least significant bits of the selected register number are considered to read a register:

• On CRTCs 0/2, registers 18-31 read as 0
• On CRTC 1, registers 18-30 read as 0, register 31 reads as &FF

On CRTCs 3/4, only the 3 least significant bits of the selected register number are considered to read a register, according to the following table:

CRTC register differences

CRTC types 3 and 4 are identical in every way, except for the unlocking mechanism, split screen, hardware soft scroll and 8-bit printer port functionalities specific to the ASIC.

R10/R11 on ASIC/Pre-ASIC

The cursor raster registers R10/R11 act as status registers when read on CRTCs 3/4. They behave as normal cursor raster registers upon write.

Horizontal and Vertical Sync (R3)

Type 0:

• Bits 7..4 define Vertical Sync Width. If 0 is programmed this gives 16 lines of VSYNC.
• Bits 3..0 define Horizontal Sync Width. If 0 is programmed no HSYNC is generated (and therefore, no interrupts).

Type 1:

• Bits 7..4 are ignored. Vertical Sync is fixed at 16 lines.
• Bits 3..0 define Horizontal Sync Width. If 0 is programmed no HSYNC is generated (and therefore, no interrupts).

Type 2:

• Bits 7..4 are ignored. Vertical Sync is fixed at 16 lines.
• Bits 3..0 define Horizontal Sync Width. If 0 is programmed this gives a HSYNC width of 16.

Types 3/4:

• Bits 7..4 define Vertical Sync Width. If 0 is programmed this gives 16 lines of VSYNC.
• Bits 3..0 define Horizontal Sync Width. If 0 is programmed this gives a HSYNC width of 16.

Interlace and Skew (R8)

Types 0/3/4:

• Bits 7..6 define the skew (delay) of the CUDISP signal (00 = Non-skew ; 01 = One-character skew ; 10 = Two-character skew ; 11 = Non-output).
• Bits 5..4 define the skew (delay) of the DISPTMG signal (00 = Non-skew ; 01 = One-character skew ; 10 = Two-character skew ; 11 = Non-output).
• Bits 3..2 are ignored.
• Bits 1..0 define the interlace mode (00 = No Interlace ; 01 = Interlace Sync ; 10 = No Interlace ; 11 = Interlace Sync and Video).

Types 1/2:

• Bits 7..2 are ignored.
• Bits 1..0 define the interlace mode.

R31 on Type 1

R31 is described in the UM6845R documentation as "Dummy Register".

Its use is described in the documentation for the Rockwell R6545 in combination with R18, R19 and R8 and the Status Register.

In the UM6845R it appears to have no effect. Reading and writing does nothing. Reading it returns &FF.

R31 doesn't exist on CRTCs 0/2/3/4.

Status register on Type 1

The UM6845R has a status register that can be read using port &BExx.

Bit 6 is set to 1 if there is a strobe input to the /LPEN signal. It is cleared to 0 when either R17 or R16 (LPEN address) of the CRTC are read. It signals there is a valid LPEN input. On Kevin Thacker's CPC with UM6845R, it is triggered at power on, R17 and R16 have the values 0 when read.

Bit 5 is set to 1 when CRTC is in "vertical blanking". Vertical blanking is when the vertical border is active. i.e. VCC>=R6.

It is cleared when the frame is started (VCC=0). It is not directly related to the DISPTMG output (used by the CPC to display the border colour) because that output is a combination of horizontal and vertical blanking. This bit will be 0 when pixels are being displayed.

All the other bits read as 0 and don't have any function.

CRTC Type Detection

10 MODE 1:' Reinitialize screen
20 OUT &BC00,31:IF INP(&BF00)=255 THEN PRINT"crtc 1":END
30 OUT &BC00,12:IF INP(&BF00)=0 THEN PRINT"crtc 2":END
40 OUT &BC00,20:IF INP(&BF00)=0 THEN PRINT"crtc 0":END
50 PRINT"crtc 3/4"

Distinguishing between CRTCs 3 and 4 can be done by trying to unlock the ASIC or by testing the PPI chip. On ASIC, if PPI Port B is set as output it will behave the same as input.

CRTC Timing Diagrams

Internal Counters

When IVM mode is activated, VLC continues to increment normally. However, RA is not identical to VLC anymore. Instead, VLC is considered shifted left by 1 bit, and bit0 represents the parity of the field (even/odd).

CRTC counter differences

MA buffering

No matter its type, the CRTC never buffers any of its counters, except for the video pointer MA. The buffer MA' is needed because MA has to be reloaded at the beginning of every raster line.

At the end of the display of the last raster line of each character line (ie. when HCC=R1 and VLC=R9), MA' captures the current value of MA.

CRTC 2 is the exception: at the end of the display of the last raster line of the frame, MA' captures R12/R13 instead of MA.

MA reload

On CRTCs 0/3/4, at the beginning of the first raster line of the frame, MA and MA' are loaded with R12/R13. Otherwise, MA is loaded with MA'.

On CRTC 2, at the beginning of every raster line of the frame (including the first one), MA is loaded with MA'.

On CRTC 1, at the beginning of every raster line of the first character line of the frame (ie. when VCC=0), MA is loaded with R12/R13 instead of MA'. This is a major source of incompatibility if the programmer does not take care. In demos and games, to be compatible with all CRTCs, program R12/R13 only when VCC≠0. This will then take effect at the next CRTC frame start.

Rupture For Dummies (R5 bug)

CRTC 1 has a bug that occurs when R5 is updated with a non-zero value when HCC=R0 and VLC≠R9, but only when R5 was previously 0. This changes the MA update source to R12/R13 instead of MA'. The CRTC then loads R12/R13 into MA at the beginning of every scanline, regardless of the VCC value.

This R5 bug also messes with the frame parity management. However, it is possible to fix the parity of the frame by activating/deactivating the IVM interlace mode.

The vertical adjustment operates normally after the RFD is triggered. If vertical adjustment is not needed, R5 can be reset at any time after the RFD is activated.

This CRTC bug divides the CPC demoscene community, with some considering it fully understood, while others find it still perplexing as it seems like the bug itself is bugged.

This effect is used in the DSC4 demo.

VSC (C3h) overflow

During a VSYNC on CRTCs 0/3/4, if VSYNC Width (R3h) is changed with a value less than the current VSC, then VSC overflows and will count up to its maximum value (15) before looping back and counting up again until it reaches the new value of R3h.

On CRTCs 1/2, the VSYNC width is fixed to 16 characters. It is not possible to modify it. Therefore, VSC cannot be overflowed.

HSC (C3l) overflow

During an HSYNC, if HSYNC Width (R3l) is changed with a value less than the current HSC, then HSC overflows and will count up to its maximum value (15) before looping back and counting up again until it reaches the new value of R3l.

The only exception is for CRTC 1 with a value of 0, which immediately cancels the current HSYNC.

VCC (C4) overflow

On all CRTCs, if Vertical Total (R4) is changed with a value less than VCC, then:

• if this update was done when VCC < R4, then VCC overflows and will count up to its maximum value (127) before looping back and counting up again until it reaches the new value of R4
• if this update was done when VCC = R4, the current character line was already decided to be the last one of the current frame. No update to R4 will make the CRTC change its mind for the current frame

The only exception when VCC = R4 is for CRTC 1 with a value of 0, which will cause VCC to overflow.

HCC (C0) overflow

If Horizontal Total (R0) is changed with a value less than the current HCC, then:

• on CRTCs 0/1/2, HCC overflows and will count up to its maximum value (255) before looping back and counting up again until it reaches the new value of R0
• on CRTCs 3/4, the current line is considered finished and HCC is immediately reset to 0 on the next line

VLC (C9) overflow

If Number of Scan Lines (R9) is changed with a value less than the current VLC, then:

• on CRTCs 0/1/2, VLC overflows and will count up to its maximum value (31) before looping back and counting up again until it reaches the new value of R9
• on CRTCs 3/4, the current line is considered the last one of this CRTC character and VLC will reset to 0 on the next line

As an exception, on CRTCs 0/2, if VLC is modified during the last frame line, then the updated value will not be considered for the current frame.

VTAC (C5/C9) overflow

During vertical adjustment mode, if Vertical Total Adjust (R5) is changed with a value less than the current VTAC, then:

• on CRTCs 0/1/2, VTAC overflows and will count up to its maximum value (31) before looping back and counting up again until it reaches the new value of R5
• on CRTCs 3/4, the current line is considered the last one of the current frame and vertical adjustment will end

As an exception, on CRTCs 0/2, if VTAC is modified during the last frame line, then the updated value will not be considered for the current frame.

Vertical Adjustment mode

On CRTCs 3/4, this mode does not increment VCC, so VCC remains equal to R4.

On CRTC 0, this mode increments VCC, causing it to exceed R4, but this increment occurs only once.

On CRTCs 1/2, this mode increments VCC, causing it to exceed R4, and this increment can happen multiple times depending on the values of R5 and R9.

Also, only CRTCs 1/2 have a dedicated C5 counter. On CRTCs 0/3/4, during Vertical Adjustment, C9 has to fullfil the VTAC role which means that it cannot fullfil its VLC role. This impacts address generation as R9 is not considered anymore.

Counter freezes

On CRTCs 1/2/3/4, R0 accepts all values without causing any problems for counters.

On CRTC 0:

• Setting R0 to 0 will cause numerous issues that stem from the fact that VLC is frozen. As HCC never reaches 1, the logic that increments VLC is never triggered.
• The logic that triggers vertical adjustment is broken if R0<2.

Block Diagrams

Hitachi

UMC

Motorola

CRTC-II (aka Type 5)

The HD6345 datasheet states it is upward-compatible with the HD6845S in pin and software.

This chip was never used by Amstrad. However, some CPC enthusiasts have replaced the original CRTC chip in their CPC with this one.

With this chip, split-screen becomes easy: Split-screen in BASIC. And 3 new graphics modes (160x100x16, 320x100x4, 640x100x2) are available: New graphics modes in BASIC.

This is the cheapest way to upgrade the CPC's graphics capabilities, costing only 1.29€. Source

Datasheets

Used by Amstrad

• HD6845S (Hitachi) aka Type 0
• UM6845 (UMC) aka Type 0
• UM6845R (UMC) aka Type 1
• MC6845 (Motorola) aka Type 2
• AMS40489 (Amstrad) aka Type 3 (ASIC)
• AMS40226 (Amstrad) aka Type 4 (Pre-ASIC)