Changes
/* TODO : Z80 testbench */
Inc_WZ register : take a look at [[http://www.righto.com/2014/10/how-z80s-registers-are-implemented-down.html § The WZ temporary registers]. It's a tmp internal register in fact.
===== Some bad instruction timing analyses analysis =====
Based on [[http://www.winape.net/ WinAPE>download>Plus test>plustest.dsk]] testbench, mapped using [[http://clrhome.org/table/ Z80 instruction set - ClrHome]], instruction described then in [[http://www.zilog.com/docs/z80/um0080.pdf Z80 doc]], against [[http://www.winape.net/ WinAPE]] passing testbench timing.
{| class="wikitable"
FD CB codes : all ko
===== Some bad instruction analyses analysis =====
Based on [[https://cpcrulez.fr/applications_CPM-util-zexall.htm Zexall: Z80 instruction set exerciser]], running fine in JavaCPC.
====== ED A9 cpd(r) / ED A1 cpi(r) ======
