Changes
/* Some bad instruction timing analyses */
! Hex !! Inst !! CPC timing !! MEM_wr:quick !! MEM_wr:slow !! remark
|-
| 02 || LD (BC),A || 2 || 2 || 3 || Normaly MEM_WR access is not prolongated.
This instruction should certainly launch write since first step.
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| 10 || DJNZ, e || 4/3 || 4/2 || 4/2
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| 12 || LD (DE), A || 2 || || 3
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| 22 || LD (nn), HL || 5 || 4 || 6|| In fact this instruction does launch two MEM_WR,and seems prolongated one more times.Quick is correctly implemented here.
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| 2A || LD HL,(nn) || 5 || 4 || 4 || In fact this instruction does launch two MEM_WRnot used by here,and shall be prolongated two timesit seems correct following doc : 4+3+3+3+3=16, 16/4=4.Damn
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| 32 || LD (nn), A || 4 || || 5|| 4+3+3+3=13<4*4, is MEM_WR prologation less that 4T ?
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| 34 || INC (HL) || 3 || || 4|| 4+4+3=11<3*4, is MEM_WR prologation less that 4T ? equals 1T ?
|-
| 35 || || 3 || || 4
| C4 || || 3/5 || || 3/6
|-
| C5 || PUSH bc || 4 || 3 || 4|| PUSH qq (same as F5)
|-
| C7 || || 4 || 3 || 3
| D4 || || 3/5 || || 3/6
|-
| D5|| PUSH de || 4 || 3 || 4|| PUSH qq (same as F5)
|-
| D7 || || 4 || 3 || 3
| E4 || || 3/5 || || 3/6
|-
| E5 || PUSH hl || 4 || 3 || 4PUSH qq (same as F5)
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| E7 || || 4 || 3 || 3
| F4 || || 3/5 || || 3/6
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| F5 || PUSH af || 4 || 3 || || PUSH qq, 5+3+3=11<3*4, is MEM_WR prologation effective two times here 1T+1T ? yes : pushing a register pair here
|-
| F7 || || 4 || 3 || 3
