Changes
/* Some bad instruction timing analysis */
! Hex !! Inst !! CPC timing !! MEM_wr:quick !! MEM_wr:slow !! remark
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| 02 || LD (BC), A || 2 || || 3 || Normaly MEM_WR access is not prolongatedFixed on r005.This instruction should certainly launch write since first step8.16c3
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| 10 || DJNZ, e || 4/3 || 4/2 || 4/2
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| 12 || LD (DE), A || 2 || || 3|| Fixed on r005.8.16c3
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| 22 || LD (nn), HL || 5 || 4 || 6 || In fact this instruction does launch two MEM_WR,and seems prolongated one more timesFixed on r005.Quick is correctly implemented here8.16c3
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| 2A || LD HL, (nn) || 5 || 4 || 4 || MEM_WR not used by here, it seems correct following doc : 4+3+3+3+3=16, 16/4=4. Damn
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| 32 || LD (nn), A || 4 || || 5 || 4+3+3+3=13<4*4, is MEM_WR prologation less that 4T ?Fixed on r005.8.16c3
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| 34 || INC (HL) || 3 || || 4 || 4+4+3=11<3*4, is MEM_WR prologation less that 4T ? equals 1T ?Fixed on r005.8.16c3
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| 35 || || 3 || || 4|| Fixed on r005.8.16c3
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| 36 || || 3 || || 4|| Fixed on r005.8.16c3
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| 70 || || 2 || || 3|| Fixed on r005.8.16c3
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| 71 || || 2 || || 3|| Fixed on r005.8.16c3
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| 72 || || 2 || || 3|| Fixed on r005.8.16c3
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| 73 || || 2 || || 3|| Fixed on r005.8.16c3
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| 74 || || 2 || || 3|| Fixed on r005.8.16c3
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| 75 || || 2 || || 3|| Fixed on r005.8.16c3
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| 77 || || 2 || || 3|| Fixed on r005.8.16c3
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| C0 || || 2/4 || 2/3 || 2/3
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| C4 || || 3/5 || || 3/6|| Fixed on r005.8.16c3
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| C5 || PUSH bc || 4 || 3 || || PUSH qq (same as F5), ok using MEM_wr:low
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| C7 || || 4 || 3 || 3|| Fixed on r005.8.16c3
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| C8 || || 4/2 || 3/2 || 3/2
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| CC || || 5/3 || 5/3 || 6/3|| Fixed on r005.8.16c3
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| CD || || 5 || || 6|| Fixed on r005.8.16c3
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| CF || || 4 || 3 || 3|| Fixed on r005.8.16c3
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| D0 || || 2/4 || 2/3 || 2/3
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| D4 || || 3/5 || || 3/6|| Fixed on r005.8.16c3
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| D5|| PUSH de || 4 || 3 || || PUSH qq (same as F5), ok using MEM_wr:low
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| D7 || || 4 || 3 || 3|| Fixed on r005.8.16c3
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| D8 || || 4/2 || 3/2 || 3/2
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| DC || || 5/3 || || 6/3|| Fixed on r005.8.16c3
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| DF || || 4 || 3 || 3|| Fixed on r005.8.16c3
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| E0 || || 2/4 || 2/3 || 2/3
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| E3 || || 6 || 5 || 6|| Fixed on r005.8.16c3
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| E4 || || 3/5 || || 3/6|| Fixed on r005.8.16c3
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| E5 || PUSH hl || 4 || 3 || PUSH qq (same as F5), ok using MEM_wr:low
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| E7 || || 4 || 3 || 3|| Fixed on r005.8.16c3
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| E8 || || 4/2 || 3/2 || 3/2
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| EC || || 5/3 || || 6/3|| Fixed on r005.8.16c3
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| EF || || 4 || 3 || 3|| Fixed on r005.8.16c3
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| F0 || || 2/4 || 2/3 || 2/3
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| F4 || || 3/5 || || 3/6|| Fixed on r005.8.16c3
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| F5 || PUSH af || 4 || 3 || || PUSH qq, 5+3+3=11<3*4, is MEM_WR prologation effective two times here 1T+1T ? yes : pushing a register pair here, ok using MEM_wr:low
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| F7 || || 4 || 3 || 3|| Fixed on r005.8.16c3
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| F8 || || 4/2 || 3/2 || 3/2
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| FC || || 5/3 || || 6/3|| Fixed on r005.8.16c3
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| FF || || 4 || 3 || 3|| Fixed on r005.8.16c3
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|}
