Changes
Z80
,/* Oddities */
* While the syntax of ADD, ADC and SBC instructions all explicitely mention the A register, the SUB instruction does not mention it.
* The 16-bit commands ADD HL,ss, ADC HL,ss and SBC HL,ss exist but not the command SUB HL,ss.
* The values of F5 and F3 following an SCF or CCF instruction depend on whether the preceding instruction modified the flags or not.[https://github.com/hoglet67/Z80Decoder/wiki/Undocumented-Flags Source]
* The BIT b,(HL) instruction exposes certain bits of the internal register WZ to the undocumented flags F5 and F3. [https://zx-pk.ru/attachment.php?attachmentid=2989 Source]
* NMOS Z80 suffers a problem whereby LD A,I and LD A,R record the state of IFF2 after it has been reset if an interrupt is delivered during that instruction. [https://sinclair.wiki.zxnet.co.uk/wiki/Z80#LD_A,I_and_LD_A,R_bug Source]
