Changes
Z80
,/* Oddities */
* The values of F5 and F3 following an SCF or CCF instruction depend on whether the preceding instruction modified the flags or not.
* The BIT b,(HL) instruction exposes certain bits of the internal register WZ to the undocumented flags F5 and F3. [https://zx-pk.ru/attachment.php?attachmentid=2989 Source]
* NMOS Z80 suffers a problem whereby LD A,I and LD A,R record the state of IFF2 after it has been reset if an interrupt is delivered during that instruction.[https://sinclair.wiki.zxnet.co.uk/wiki/Z80#LD_A,I_and_LD_A,R_bug Source]
* Z80 is always NMOS on CPC and Plus machines. [https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/z80-cpu-nmos-or-cmos/ Source]
