Difference between revisions of "ASIC"

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* REPEAT Loops cannot be nested . Only one is allowed to be active per instruction stream at any time.
 
* REPEAT Loops cannot be nested . Only one is allowed to be active per instruction stream at any time.
 
* REPEAT 0 and PAUSE 0 instructions have no effect, i.e. they are equivalent to NOP.
 
* REPEAT 0 and PAUSE 0 instructions have no effect, i.e. they are equivalent to NOP.
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* Control group (4xxxh) instructions can be logically ORed to produce more complex instructions, e.g. INT|STOP = 4030h = Interrupt and stop.
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* Control group (4xxxh) instructions can be logically ORed to produce more complex instructions, e.g. INT|STOP = 4030h = Interrupt and Stop.
 
* The STOP instruction will leave the source address register pointing to the next instruction, so that the instruction stream can be continued after CPU intervention.
 
* The STOP instruction will leave the source address register pointing to the next instruction, so that the instruction stream can be continued after CPU intervention.
 
* The argument field (N) of the REPEAT instruction is actually the number of times the loop is taken. The block of code between REPEAT and LOOP instructions is therefore executed N+1 times.
 
* The argument field (N) of the REPEAT instruction is actually the number of times the loop is taken. The block of code between REPEAT and LOOP instructions is therefore executed N+1 times.

Revision as of 01:39, 5 July 2024

Application-Specific Integrated Circuit (ASIC)

An ASIC is an especially manufactured custom chip designed to fulfill special functions.

The main reason is to perform special tasks or combine different electronic components into a single Integrated Circuit (chip). This chip is not commonly available (COTS), but has to be ordered as a genuine part, prices dictated by the seller.

After a seller goes out of business or stops supporting a product line, before IPs (Instruction set Processors) like CPLD or FPGA, they essentially became unavailable. Commodore used a plethora of ASICs in their machines (VIC, SID, PAULA,......); MSX or the IBM PC/XT/AT were the opposite in using only COTS components, making it easy for third parties to offer parts (or to re-build and repair the computers for as long as the COTS chip was still available or a backwards-compatible component exists).


Amstrad Custom chips

The Amstrad CPC used one custom chip: the video Gate Array (also called VGA – no connection with the Video PC standard).

Latter CPC cost down series included a "pre-ASIC"-called ASIC to merge the VGA and the CRTC.

The Amstrad Plus included a "second heart" simply referred as the ASIC. 

CPC+ ASIC's part number is 40489


Emulated chips

CPC+ ASIC emulates the following chips :


New features

This Amstrad Plus ASIC performs many additional features that the old CPC series couldn't: the "Plus Features".

  • Hardware Sprites.
  • Soft scrolling (in complement with register 12&13 of the CRTC)
  • Screen splitting
  • Programmable and vectorised interrupts
  • DMA sound channels
  • Specific ROM switching
  • 8-bit printer port (with bit3 of CRTC register 12)


DMA commands

The available commands are :

Code Mnemonic Description
0RDDh LOAD R,D Load 8 bit data D to PSG register R (0 < R ≤ 15)
1NNNh PAUSE N Pause for N prescaled ticks (0 < N ≤ 4095)
2NNNh REPEAT N Set loop counter to N for this stream (0 < N ≤ 4095) and mark next instruction as loop start
3xxxh (reserved) Do not use
4000h NOP No operation (64us idle)
4001h LOOP If loop counter non zero, loop back to the first instruction after REPEAT instruction and decrement loop counter
4010h INT Interrupt the CPU
4020h STOP Stop processing the sound list

Note that :

  • REPEAT Loops cannot be nested . Only one is allowed to be active per instruction stream at any time.
  • REPEAT 0 and PAUSE 0 instructions have no effect, i.e. they are equivalent to NOP.
  • Control group (4xxxh) instructions can be logically ORed to produce more complex instructions, e.g. INT|STOP = 4030h = Interrupt and Stop.
  • The STOP instruction will leave the source address register pointing to the next instruction, so that the instruction stream can be continued after CPU intervention.
  • The argument field (N) of the REPEAT instruction is actually the number of times the loop is taken. The block of code between REPEAT and LOOP instructions is therefore executed N+1 times.


Known Flaws

The Amstrad Plus ASIC improved a lot of the old CPC's capability. Yet this was a bit flawed.

  • Despite removing some tasks from the CPU (Z80), ASIC registers are mapped onto memory from #4000 to #7FFF range prior to other type of memory (RAM or ROM). That means this memory range is not accessible when ASIC registers are paged.
  • PPI emulation is not correct as the original 8255 does not need validation. On ASIC emulation, this validation is needed so some programs written for "old CPCs" will not be able to get keyboard state.
  • Z80 IM2 mode is bugged. In this mode, the Z80 I register gives the high word for vector table. ASIC gives the low word from IVR and the devices that generate interrupt (raster and DMAs channels). ASIC may generate a bad values and the raster interrupt routine is called instead of DMA0 routine if the Z80 is running particular portions of memory. See Plus Vectored Interrupt Bug for more details.
  • There is a conflict between programmable interrupts and some CRTC settings (line screen split). That will cause the RAM refresh to stop and the memory content will be quickly corrupted causing machine crash.
  • Reducing horizontal blanking could cause another internal conflict when using DMA lists. In the worst case, this conflict can cause irreversible damage to the ASIC.
  • Original CPC colors emulation is not correct.


Internal Links


External Links


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