Difference between revisions of "ASIC"

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Application-Specific Integrated Circuit (ASIC)
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'''Application-Specific Integrated Circuit''' (ASIC)
  
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An ASIC is an especially manufactured custom chip designed to fulfil special functions.
+
An '''ASIC''' is an especially manufactured custom chip designed to fulfill special functions.
  
−
The main reason is to perform special tasks or combine different electronic components into a single Integrated Circuit (chip).
+
The main reason is to perform special tasks or combine different electronic components into a single Integrated Circuit (chip). This chip is not commonly available ([[COTS]]), but has to be ordered as a genuine part, prices dictated by the seller.
 +
 
 +
After a seller goes out of business or stops supporting a product line, before IPs (Instruction set Processors) like [[CPLD]] or [[FPGA]], they essentially became unavailable. [[Commodore_64#ICs|Commodore]] used a plethora of ASICs in their machines (VIC, SID, PAULA,......); [[MSX]] or the [[IBM PC]]/XT/AT were the opposite in using only [[COTS]] components, making it easy for third parties to offer parts (or to re-build and repair the computers for as long as the COTS chip was still available or a backwards-compatible component exists).
 +
 
 +
<br>
  
 
==Amstrad Custom chips==
 
==Amstrad Custom chips==
Line 9: Line 13:
 
The Amstrad CPC used one custom chip: the video [[Gate Array]] (also called VGA – no connection with the Video PC standard).
 
The Amstrad CPC used one custom chip: the video [[Gate Array]] (also called VGA – no connection with the Video PC standard).
  
−
Latter [[CPC]] cost down series included a "pre-ASIC" to merge the VGA and the CRTC.
+
Latter [[CPC]] cost down series included a "pre-ASIC"-called ASIC to merge the VGA and the [[CRTC]].
  
 
The Amstrad [[Plus]] included a "second heart" simply referred as the ASIC.
 
The Amstrad [[Plus]] included a "second heart" simply referred as the ASIC.
  
 
  CPC+ ASIC's part number is 40489
 
  CPC+ ASIC's part number is 40489
 +
 +
<br>
  
 
==Emulated chips==
 
==Emulated chips==
  
−
CPC+ ASIC emulated the following chips :
+
CPC+ ASIC emulates the following chips:
  
−
*CRTC 6845
+
* [[CRTC]] 6845
−
*Gate Array
+
* [[Gate Array]]
−
*PAL (memory paging)
+
* [[PAL16L8|PAL]] (128K RAM paging)
−
*8255 PPI
+
* [[8255|8255 PPI]]
 +
* Printer Port Data and Strobe
 +
* Floppy Motor enable [[flip-flop]], Floppy Address decoding (FDC chip Select)
 +
 
 +
<br>
  
 
==New features==
 
==New features==
  
−
This Amstrad Plus ASIC perform many additional features that the old CPC series couldn't: the "Plus Features".
+
This Amstrad Plus ASIC performs many additional features that the old CPC series couldn't: the "Plus Features".
  
 
*Hardware Sprites.
 
*Hardware Sprites.
Line 34: Line 44:
 
*DMA sound channels
 
*DMA sound channels
 
*Specific ROM switching
 
*Specific ROM switching
 +
*8-bit printer port (with bit3 of CRTC register 12)
  
 +
<br>
 +
 +
== Soft Scroll ==
 +
 +
The 8-bit register SSCR (at address 6804h) controls soft scrolling by pixels rather than by characters. Setting this register to 0 (the default value at power-up) disables the soft scroll feature. The soft scrolling mechanism affects the entire main screen, regardless of the split screen feature, but does not affect sprites.
 +
* Bit3..0 of SSCR defines a horizontal delay between 0 and 15 high-resolution (mode 2) pixels, shifting the screen image to the right by the programmed value. This causes pixels to be lost behind the right border and random data to appear on the left. Also the programmer must ensure that the delay value is a multiple of the number of bits per pixel.
 +
* Bit6..4 of SSCR is added to the least significant 3 bits of the scan line address, determining which of the eight 2k blocks contains the data for the first scan line on the screen. This shifts the display up by the programmed number of scan lines, causing the first lines to be lost and extra lines to appear at the bottom.
 +
* Bit7 of SSCR, when set, extends the border to cover the first 2 bytes (16 high-resolution pixels) of each scan line, masking bad data caused by the horizontal soft scroll. When using horizontal soft scroll, always set this bit to maintain consistent screen width.
 +
 +
<br>
 +
 +
== Split Screen ==
 +
 +
The 8-bit register SPLT (at address 6801h) specifies the scan line where the screen split occurs. Setting this register to 0 (the default value at power-up) disables the split screen feature.
 +
 +
The 16-bit register SSA (high byte at address 6802h and low byte at address 6803h) defines the starting address in memory for displaying the lower part of the screen. SSA works similarly to the duo R12/R13 in the CRTC. This configuration allows the lower part of the screen to be sourced from a different memory area and be scrolled independently. However, note that the soft scrolling register SSCR acts on the whole screen.
 +
 +
<br>
 +
 +
== Programmable Raster Interrupt ==
 +
 +
The 8-bit memory-mapped register PRI (at address 6800h) specifies the scan line where the interrupt occurs. The interrupt will occur at the end of that scan line. Setting this register to 0 (the default value at power-up) reverts to the classic R52 raster interrupt system of the [[Gate Array]] instead.
 +
 +
PRI can be reprogrammed as required to produce multiple interrupts per frame.
 +
 +
Additionally, on Amstrad Plus, we have multiple sources of interrupts as each DMA sound channel can trigger an interrupt.
 +
 +
<br>
 +
 +
== Vectored Interrupt ==
 +
 +
In this mode, interrupts are prioritized in a fixed sequence. The raster interrupt has the highest priority, followed by DMA channels 2 down to 0 respectively.
 +
 +
The register IVR (at address 6805h) supplies the top 5 bits of the vector. It is undefined at reset except that bit0 will be set to 1. Therefore, before placing the CPU in vectored interrupt, always set up the IVR so that the top 5 bits are defined.
 +
 +
Bit0 of the IVR controls whether DMA channel interrupts are automatically cleared.
 +
 +
<br>
 +
 +
== DMA commands ==
 +
 +
Each DMA channel fetch one 16-bit instruction during horizontal retrace time. Once the 3 instructions have been captured, they are then executed sequentially.
 +
 +
These instructions are encoded in little-endian (LSB byte first). They must be located in Base 64k RAM and aligned to word boundary (the address of first byte must be even).
 +
 +
The available commands are:
 +
 +
{| class="wikitable"
 +
|-
 +
! Code
 +
! Mnemonic
 +
! Description
 +
|-
 +
| 0RDDh
 +
| LOAD R,D
 +
| Load 8 bit data D to PSG register R (0 < R ≤ 15)
 +
|-
 +
| 1NNNh
 +
| PAUSE N
 +
| Pause for N prescaled ticks (0 < N ≤ 4095)
 +
|-
 +
| 2NNNh
 +
| REPEAT N
 +
| Set loop counter to N for this stream (0 < N ≤ 4095) and mark next instruction as loop start
 +
|-
 +
| 3xxxh
 +
| (reserved)
 +
| Do not use
 +
|-
 +
| 4000h
 +
| NOP
 +
| No operation (64µs idle)
 +
|-
 +
| 4001h
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| LOOP
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| If loop counter non zero, loop back to the first instruction after REPEAT instruction and decrement loop counter
 +
|-
 +
| 4010h
 +
| INT
 +
| Interrupt the CPU
 +
|-
 +
| 4020h
 +
| STOP
 +
| Stop processing the sound list
 +
|}
 +
 +
Note that:
 +
 +
* REPEAT Loops cannot be nested. Only one is allowed to be active per instruction stream at any time.
 +
* REPEAT 0 and PAUSE 0 instructions have no effect, i.e. they are equivalent to NOP.
 +
* Control group (4xxxh) instructions can be logically ORed to produce more complex instructions, e.g. INT|STOP = 4030h = Interrupt and Stop.
 +
* The STOP instruction will leave the source address register pointing to the next instruction, so that the instruction stream can be continued after CPU intervention.
 +
* The argument field (N) of the REPEAT instruction is actually the number of times the loop is taken. The block of code between REPEAT and LOOP instructions is therefore executed N+1 times.
 +
 +
 +
A DMA control and status register (DCSR) controls which channels are currently enabled, and also tells the CPU which channel is interrupting:
 +
* The channel enable bits in this register enable each "DMA" channel separately, and can be set by the CPU, and cleared by either the CPU, a STOP instruction, or power on rest.
 +
* The interrupt bits are set when a channel is requesting an interrupt, and cleared when the CPU writes a "1" to the appropriate bit.
 +
* The INT signal of the ASIC is the compositing of all the interrupt bits of DCSR by using the AND function. INT is "0" if at least one of the interrupt bits is "0".
 +
 +
<br>
  
 
== Known Flaws==
 
== Known Flaws==
Line 41: Line 153:
 
Yet this was a bit flawed.
 
Yet this was a bit flawed.
  
−
*Despite removing some tasks from the CPU ([[Z80]]), ASIC registers are mapped onto memory from #4000 to #7FFF range prior to other type of memory (RAM or ROM).That means this memory range is not accessible when ASIC registers are paged.
+
*Despite removing some tasks from the CPU ([[Z80]]), ASIC registers are mapped onto memory from #4000 to #7FFF range prior to other type of memory (RAM or ROM). That means this memory range is not accessible when ASIC registers are paged.
  
−
*PPI emulation is not correct as the original 8255 does not need validation.On ASIC emulation , this validation is needed so some programs written for "old CPCs" will not be able to get keyboard state.
+
*PPI emulation is not correct as the original 8255 does not need validation. On ASIC emulation, this validation is needed so some programs written for "old CPCs" will not be able to get keyboard state.
  
−
*Z80 IM2 mode is bugged.In this mode , the Z80 I register gives the high word for vector table.ASIC gives the low word from IVR and the devices that generate interrupt (raster and DMAs channels).ASIC generates sometimes a bad values and the raster interrupt routine is called instead of DMA0 routine.The reasons of this bug are not known.
+
*Z80 IM2 mode is bugged. In this mode, the Z80 I register gives the high word for vector table. ASIC gives the low word from IVR and the devices that generate interrupt (raster and DMAs channels). ASIC may generate a bad values and the raster interrupt routine is called instead of DMA0 routine if the Z80 is running particular portions of memory. See [[Plus Vectored Interrupt Bug]] for more details.
  
−
*There is a conflict between programmable interrupts and some CRTC settings (line screen split).That will cause the RAM refresh to stop and the memory content will be quickly corrupted causing machine crash.
+
*There is a conflict between programmable interrupts and some CRTC settings (line screen split). That will cause the RAM refresh to stop and the memory content will be quickly corrupted causing machine crash.
  
−
*Reducing Horizontal BLanking could cause another internal conflict when using DMA lists.In the worst case , this conflict can cause irreversible damage to the ASIC.
+
*Reducing horizontal blanking could cause another internal conflict when using DMA lists. In the worst case, this conflict can cause irreversible damage to the ASIC.
  
 
*Original CPC colors emulation is not correct.
 
*Original CPC colors emulation is not correct.
 +
 +
<br>
  
 
==Internal Links==
 
==Internal Links==
Line 57: Line 171:
 
*[[Arnold V specs]]
 
*[[Arnold V specs]]
 
*[[Arnold V Specs Revised]]
 
*[[Arnold V Specs Revised]]
 +
 +
*[[Default I/O Port Summary|ASIC I/O page]]
 
*[[Programming:Unlocking ASIC]]
 
*[[Programming:Unlocking ASIC]]
 
*[[B-ASIC]]
 
*[[B-ASIC]]
Line 62: Line 178:
 
*[[CRTC]]
 
*[[CRTC]]
 
*[[Gate Array]]
 
*[[Gate Array]]
 +
 +
<br>
  
 
==External Links==
 
==External Links==
  
−
*[http://en.wikipedia.org/wiki/Application-specific_integrated_circuit ASIC at Wikipedia]
+
*[http://en.wikipedia.org/wiki/Application-specific_integrated_circuit ASIC at Wikipedia] General information on ASICs.
−
General information on ASICs.
+
  
 +
*[http://www.cpctech.org.uk/docs/arn5new.html Asic and Plus features at Unofficial CPC ressources 1.4]
 +
*[http://www.cpctech.org.uk/docs/arnold5a.html Asic and Plus features at Unofficial CPC ressources 1.5]
 +
*[http://www.cpctech.org.uk/docs/cpcplus.html Extra Plus Hardware Information]
 +
*[http://quasar.cpcscene.net/doku.php?id=assem:asic Quasar ASIC documentation (in french)]
  
−
*[http://www.kjthacker.f2s.com/docs/arn5new.html Asic and Plus features at Unofficial CPC ressources 1.4]
+
<br>
−
*[http://www.kjthacker.f2s.com/docs/arnold5a.html Asic and Plus features at Unofficial CPC ressources 1.5]
+
−
*[http://www.kjthacker.f2s.com/docs/cpcplus.html Extra Plus Hardware Information]
+
  
−
[[Category:CPC Plus|*]][[Category:Hardware]][[Category:Programming]][[Category:Datasheet]][[Category:Graphic]]
+
[[Category:CPC Plus|*]][[Category:Electronic Component]][[Category:Programming]][[Category:Datasheet]][[Category:Graphic]]
 
[[Category:Stub]][[Category:CPC Internal Components]]
 
[[Category:Stub]][[Category:CPC Internal Components]]

Latest revision as of 10:17, 5 July 2024

Application-Specific Integrated Circuit (ASIC)

An ASIC is an especially manufactured custom chip designed to fulfill special functions.

The main reason is to perform special tasks or combine different electronic components into a single Integrated Circuit (chip). This chip is not commonly available (COTS), but has to be ordered as a genuine part, prices dictated by the seller.

After a seller goes out of business or stops supporting a product line, before IPs (Instruction set Processors) like CPLD or FPGA, they essentially became unavailable. Commodore used a plethora of ASICs in their machines (VIC, SID, PAULA,......); MSX or the IBM PC/XT/AT were the opposite in using only COTS components, making it easy for third parties to offer parts (or to re-build and repair the computers for as long as the COTS chip was still available or a backwards-compatible component exists).


Amstrad Custom chips

The Amstrad CPC used one custom chip: the video Gate Array (also called VGA – no connection with the Video PC standard).

Latter CPC cost down series included a "pre-ASIC"-called ASIC to merge the VGA and the CRTC.

The Amstrad Plus included a "second heart" simply referred as the ASIC. 

CPC+ ASIC's part number is 40489


Emulated chips

CPC+ ASIC emulates the following chips:


New features

This Amstrad Plus ASIC performs many additional features that the old CPC series couldn't: the "Plus Features".

  • Hardware Sprites.
  • Soft scrolling (in complement with register 12&13 of the CRTC)
  • Screen splitting
  • Programmable and vectorised interrupts
  • DMA sound channels
  • Specific ROM switching
  • 8-bit printer port (with bit3 of CRTC register 12)


Soft Scroll

The 8-bit register SSCR (at address 6804h) controls soft scrolling by pixels rather than by characters. Setting this register to 0 (the default value at power-up) disables the soft scroll feature. The soft scrolling mechanism affects the entire main screen, regardless of the split screen feature, but does not affect sprites.

  • Bit3..0 of SSCR defines a horizontal delay between 0 and 15 high-resolution (mode 2) pixels, shifting the screen image to the right by the programmed value. This causes pixels to be lost behind the right border and random data to appear on the left. Also the programmer must ensure that the delay value is a multiple of the number of bits per pixel.
  • Bit6..4 of SSCR is added to the least significant 3 bits of the scan line address, determining which of the eight 2k blocks contains the data for the first scan line on the screen. This shifts the display up by the programmed number of scan lines, causing the first lines to be lost and extra lines to appear at the bottom.
  • Bit7 of SSCR, when set, extends the border to cover the first 2 bytes (16 high-resolution pixels) of each scan line, masking bad data caused by the horizontal soft scroll. When using horizontal soft scroll, always set this bit to maintain consistent screen width.


Split Screen

The 8-bit register SPLT (at address 6801h) specifies the scan line where the screen split occurs. Setting this register to 0 (the default value at power-up) disables the split screen feature.

The 16-bit register SSA (high byte at address 6802h and low byte at address 6803h) defines the starting address in memory for displaying the lower part of the screen. SSA works similarly to the duo R12/R13 in the CRTC. This configuration allows the lower part of the screen to be sourced from a different memory area and be scrolled independently. However, note that the soft scrolling register SSCR acts on the whole screen.


Programmable Raster Interrupt

The 8-bit memory-mapped register PRI (at address 6800h) specifies the scan line where the interrupt occurs. The interrupt will occur at the end of that scan line. Setting this register to 0 (the default value at power-up) reverts to the classic R52 raster interrupt system of the Gate Array instead.

PRI can be reprogrammed as required to produce multiple interrupts per frame.

Additionally, on Amstrad Plus, we have multiple sources of interrupts as each DMA sound channel can trigger an interrupt.


Vectored Interrupt

In this mode, interrupts are prioritized in a fixed sequence. The raster interrupt has the highest priority, followed by DMA channels 2 down to 0 respectively.

The register IVR (at address 6805h) supplies the top 5 bits of the vector. It is undefined at reset except that bit0 will be set to 1. Therefore, before placing the CPU in vectored interrupt, always set up the IVR so that the top 5 bits are defined.

Bit0 of the IVR controls whether DMA channel interrupts are automatically cleared.


DMA commands

Each DMA channel fetch one 16-bit instruction during horizontal retrace time. Once the 3 instructions have been captured, they are then executed sequentially.

These instructions are encoded in little-endian (LSB byte first). They must be located in Base 64k RAM and aligned to word boundary (the address of first byte must be even).

The available commands are:

Code Mnemonic Description
0RDDh LOAD R,D Load 8 bit data D to PSG register R (0 < R ≤ 15)
1NNNh PAUSE N Pause for N prescaled ticks (0 < N ≤ 4095)
2NNNh REPEAT N Set loop counter to N for this stream (0 < N ≤ 4095) and mark next instruction as loop start
3xxxh (reserved) Do not use
4000h NOP No operation (64µs idle)
4001h LOOP If loop counter non zero, loop back to the first instruction after REPEAT instruction and decrement loop counter
4010h INT Interrupt the CPU
4020h STOP Stop processing the sound list

Note that:

  • REPEAT Loops cannot be nested. Only one is allowed to be active per instruction stream at any time.
  • REPEAT 0 and PAUSE 0 instructions have no effect, i.e. they are equivalent to NOP.
  • Control group (4xxxh) instructions can be logically ORed to produce more complex instructions, e.g. INT|STOP = 4030h = Interrupt and Stop.
  • The STOP instruction will leave the source address register pointing to the next instruction, so that the instruction stream can be continued after CPU intervention.
  • The argument field (N) of the REPEAT instruction is actually the number of times the loop is taken. The block of code between REPEAT and LOOP instructions is therefore executed N+1 times.


A DMA control and status register (DCSR) controls which channels are currently enabled, and also tells the CPU which channel is interrupting:

  • The channel enable bits in this register enable each "DMA" channel separately, and can be set by the CPU, and cleared by either the CPU, a STOP instruction, or power on rest.
  • The interrupt bits are set when a channel is requesting an interrupt, and cleared when the CPU writes a "1" to the appropriate bit.
  • The INT signal of the ASIC is the compositing of all the interrupt bits of DCSR by using the AND function. INT is "0" if at least one of the interrupt bits is "0".


Known Flaws

The Amstrad Plus ASIC improved a lot of the old CPC's capability. Yet this was a bit flawed.

  • Despite removing some tasks from the CPU (Z80), ASIC registers are mapped onto memory from #4000 to #7FFF range prior to other type of memory (RAM or ROM). That means this memory range is not accessible when ASIC registers are paged.
  • PPI emulation is not correct as the original 8255 does not need validation. On ASIC emulation, this validation is needed so some programs written for "old CPCs" will not be able to get keyboard state.
  • Z80 IM2 mode is bugged. In this mode, the Z80 I register gives the high word for vector table. ASIC gives the low word from IVR and the devices that generate interrupt (raster and DMAs channels). ASIC may generate a bad values and the raster interrupt routine is called instead of DMA0 routine if the Z80 is running particular portions of memory. See Plus Vectored Interrupt Bug for more details.
  • There is a conflict between programmable interrupts and some CRTC settings (line screen split). That will cause the RAM refresh to stop and the memory content will be quickly corrupted causing machine crash.
  • Reducing horizontal blanking could cause another internal conflict when using DMA lists. In the worst case, this conflict can cause irreversible damage to the ASIC.
  • Original CPC colors emulation is not correct.


Internal Links


External Links


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