Changes
/* Usage in CPC interfaces */
Used by standard [[Amstrad Serial Interface]] (and compatible) RS232 interfaces, mapped to Ports:
FBDCh Amstrad RS323 8253 Baudrate Timer 0 Channel A TX Clock (R/W)
FBDDh Amstrad RS323 8253 Baudrate Timer 1 Channel A RX Clock (R/W)
Also used by [[KDS_Electronics_Serial_Interface|KDS Serial Interface]], mapped to other Ports, and RX/TX exchanged:
FBE8h KDS RS232 8253 Baudrate Timer 0 (RX Clock) (R/W)
FBE9h KDS RS232 8253 Baudrate Timer 1 (TX Clock) (R/W)
Clock Input seems to be 2MHz, Clock output goes to a [[6850 ACIA chip]],
Clock Output may be further divided by 1, 16, or 64 in the 6850 chip
Also used by Aleste 520EX CPC clone:
F4X0h Aleste_PPIPortA_PsgPortA, Baudrate Timer 0 (RX Clock) (W)
F4X1h Aleste_PPIPortA_PsgPortA, Baudrate Timer 1 (TX Clock) (W)
F4X2h Aleste_PPIPortA_PsgPortA, Baudrate Timer 2 (FUTURE) (W)
F4X3h Aleste_PPIPortA_PsgPortA, Timer 0-2 Control Registers (W)
Clock Input for RX/TX is 4MHz, Clock output goes to a 8251 chip,
Clock Input for FUTURE is HSYNC, Clock output selects 1st/2nd color set,
the FUTURE clock is restarted via GATE=CRTC's "CURSOR" output,
All registers are write-only (/RD is wired to VCC)
PPI Port A data direction must be output,
Aleste ExtReg must enable access to 8253, and disable access to PSG
== Timer Registers ==
