Changes
== Usage in CPC interfaces ==
Used by standard [[Amstrad_Serial_Interface|AmstradSerial Interface]] (and compatible) RS232 interfaces, mapped to Ports:
FBDCh Amstrad RS323 8253 Baudrate Timer 0 Channel A TX Clock (R/W)
FBDEh Amstrad RS323 8253 Baudrate Timer 2 Channel B RX/TX Clock (R/W)
FBDFh Amstrad RS323 8253 Baudrate Timer 0-2 Control Registers (W)
Clock Input seems to be 2MHz, Clock output goes to a [[Z80 -DART /Z80-SIO chip]],
Clock Output may be further divided by 1, 16, 32, or 64 in the DART chip
Also used by [[KDS_Electronics_Serial_Interface|KDS interfaceSerial Interface]], mapped to other Ports, and RX/TX exchanged:
FBE8h KDS RS232 8253 Baudrate Timer 0 (RX Clock) (R/W)
FBEAh KDS RS232 8253 Baudrate Timer 2 (not used) (R/W)
FBEBh KDS RS232 8253 Baudrate Timer 0-2 Control Registers (W)
Clock Input seems to be 2MHz, Clock output goes to a [[6850 ACIA chip]],
Clock Output may be further divided by 1, 16, or 64 in the 6850 chip
6=Same as Mode 2
7=Same as Mode 3
0 BCD (0=normal, 1=bcd)
When used as RS232 Baudrate Generator (ie. as in the CPC), all three registers should be set to square-wave non-bcd lsb-then-msb (ie. write values 36h, 76h, and B6h to this port).
