Changes
/* PIN FUNCTIONS */
|1||1||1||INTAK||LATCH ADDRESS. This signal indicates that the bus contains a register address which should be latched in the PSG. DA7--DA0 are in the input mode.
|}
'''IOA7--IOA0 (input/output): pins 14--21 (AY-3-8910) pins 7--14 (AY-3-8912) (not provided on AY-3-8913)'''
'''IOB7--IOB0 (input/output): pins 6--13 (AY-3-8910) (not provided on AY-3-8912) (not provided on AY-3-8913) ''' '''Input/Output A7--A0, B7--B0'''
Each of these two parallel input/output ports provides 8 bits of parallel data to/from the PSG/CPU bus from/to any external devices connected to the IOA or IOB pins. Each pin is provided with an on-chip pull-up resistor, so that when in the "input" mode, all pins will read normally high. Therefore, the recommended method for scanning external switches would be to ground the input bit.
'''TEST 1: pin 39 (AY-3-8910) pin 14 (AY-3-8913) pin 2 (AY-3-8912) ''' '''TEST 2: pin 26 (AY-3-8910) pin 12 (AY-3-8913) (not connected on AY-3-8912)'''
These pins are for General Instrument test purposes only and should be left open -- do not use as tie-points.
'''Vcc: pin 40 (AY-3-8910) pin 13 (AY-3-8913) pin 3 (AY-3-8912) '''
Nominal +5Volt power supply to PSG.
'''Vss: pin 1 (AY-3-8910) pin 19 (AY-3-8913) pin 6 (AY-3-8912) '''
Ground reference for the PSG.
'''/CHIP SELECT (Input): pin 24 (AY-3-8913 only) '''
This input signal goes low to enable the PSG to read data on the data bus or write data from the data bus to one of the internal registers. For these above operations to occur, this signal must be true in addition to the current bus address being a valid PSG address. This signal must be valid for all read and write operations. This pin has an internal pull down to Vss.
