Changes
/* PIN FUNCTIONS */
== PIN FUNCTIONS ==
'''DA7--DA0 (input/output/high impedance) pins 30--37 (AY-3-8910) pins 21--28 (AY-3-8912) pins 4--11 (AY-3-8913) ''' '''Data/Address 7--0:'''
These 8 lines comprise the 8-bit bidirectional bus used by the microprocessor to send both data and addresses to the PSG and to recieve data from the PSG. In the data mode, DA7--DA0 correspond to Register Array bits B7--B0. In the address mode, DA3--DA0 select the register number (0--17 8) and a DA7-DA4 in conjunction with address inputs /A9 and A8 for the high order address (chip select).
'''A8 (input): pin 25 (AY-3-8910) pin 17 (AY-3-8912) pin 23 (AY-3-8913) ''' '''/A9 (input): pin 24 (AY-3-8910) pin 28 (AY-3-8912) (not provided on AY-3-8913)'''
'''/A9 (input): pin 24 (AY-3-8910) pin 28 (AY-3-8912) (not provided on AY-3-8913) Address 9,Address 8'''
These "extra" address bits are made available to enable the positioning of the PSG (assigning a 16 word memory space) in a total 1,024 word memory area rather than in a 256 word memory area as defined by address bits DA7--DA0 alone. If the memory size does not require the use of these extra address lines they may be left unconnected as each is provided with either an on-chip pull down (/A9) or pull-up (A8) resistor. In "noisy" environments, however, it is recommended that /A9 and A8 be tied to an external ground and +5V, respectively, if they are not to be used.
'''/RESET (input): pin 23 (AY-3-8910) pin 21 (AY-3-8913) pin 16 (AY-3-8912) '''
For initialization/power on purposes, applying a logic "0" (ground) to the /Reset pin will reset all registers to "0". The /Reset pin is provided with an on-chip pull-up resistor.
'''CLOCK (signal): pin 22 (AY-3-8910) pin 20 (AY-3-8913) pin 15 (AY-3-8912) '''
This TTL-compatible input supplies the timing reference for the Tone, Noise and Envelope Generators.
'''BDIR,BC2,BC1 (inputs): pins 27,28,29 (AY-3-8910) pins 18,19,20 (AY-3-8912) pins 2,3 (No BC2 on AY-3-8913 see below) ''' '''Bus DiRection, Bus Control 2,1'''
These bus control signals are generated directly by the CP1610 series of microprocessors to control all external and internal bus operations in the PSG. When using a processor other than the Cp1610, these signals can be provided either by comparable bus signals or by simulating the signals on I/O lines of the processor. The PSG decodes these signals as illustrated in the following:
{|{{Prettytable|width: 700px; font-size: 2em;}}|''BDIR ''||''BC2 ''||''BC1 ''||''PSG FUNCTION Function''|-|0 ||1 ||0 ||INACTIVE |-|0 ||1 ||1 ||READ FROM PSG |-|1 ||1 ||0 ||WRITE TO PSG |-|1 ||1 ||1 ||LATCH ADDRESS |}
[[Image:psg10.gif]]
'''ANALOG CHANNEL A,B,C (outputs): pins 4,3,38 (AY-3-8910) pins 5,4,1 (AY-3-8912) pins 17,15,18 (AY-3-8913)'''
Each of these signals is the output of its corresponding D/A Converter, and provides a up to 1V peak-peak signal representing the complex sound waveshape generated by the PSG.
'''IOA7--IOA0 (input/output): pins 14--21 (AY-3-8910) pins 7--14 (AY-3-8912) (not provided on AY-3-8913) '''
IOB7--IOB0 (input/output): pins 6--13 (AY-3-8910) (not provided on AY-3-8912) (not provided on AY-3-8913)
