== Pipelining ==
The 6502 CPU uses some sort Wr have to dispel the myth of pipeliningin the 6502. If an instruction does not store data we analyze its operation in memory on its last cyclehalf-cycles, the processor can fetch the opcode of the next we see that instruction while executing the last cycle. This execution is very primitive as the 6502 does not have an instruction cache nor even a prefetch queue. It relies on RAM tightly bound to hold all program informationmemory operations without any overlap between different instructions.
As an exampleEach instruction follows a rigid sequence of steps, with no ability to fetch the next instruction EOR #$FF truly takes 3 cycles:* On while executing the first cycle, current one. This means that the opcode $49 will be fetched* During the second cycle the processor decodes the opcode and fetches the parameter #$FF* On the third cycle, the processor will perform the operation and store the result CPU cannot prefetch opcodes or operands ahead of time in register A, but simultaneously it fetches the opcode for the next instructionway a pipelined architecture would.
This is If we invert our perspective and consider ϕ2 as the first half-cycle and ϕ1 as the second, it becomes evident why pipelining does not exist on the EOR instruction effectively takes only 2 cycles6502.
However, this pipelining only makes sense when looking at full cycles. If we break it down into half-cycles, there's no actual overlap. In fact, it's the other way around. If the previous instruction ends with a memory write, the CPU has to wait for a half-cycle before fetching the next instruction on the next ϕ2 half-cycle.
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