== Pipelining ==
Wr We have to dispel the myth of pipelining in the 6502. If we analyze its operation in half-cycles, we see that instruction execution is tightly bound to memory operations without any overlap between different instructions.
Each instruction follows a rigid sequence of steps, with no ability to fetch the next instruction while executing the current one. This means that the CPU cannot prefetch opcodes or operands ahead of time in the way a pipelined architecture would.