If we invert our perspective and consider ϕ2 as the first half-cycle and ϕ1 as the second, it becomes evident why pipelining does not exist on the 6502.
In fact, it's the other way around. If the previous instruction ends with a memory write, the CPU has to wait for a half-cycle before fetching being able to fetch the next instruction on the next ϕ2 half-cycle.
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