Changes
Z80
,/* Internal state */
Also note that while POP AF and EX AF,AF' modify F, they do not compute new flag values.
The explanation above is just an approximation. Latest research on the subject (May 2024) show that In fact, '''SCF/CCF instructions are unstable'''. [https://github.com/hoglet67/Z80Decoder/wiki/Unstable-CCF-SCF-Behaviour Source] As of Oct 2024, this is now fully understood. Everything happens due to the fact that two internal buses HBUS and LBUS, to which the contents of registers A and F are issued at the beginning of the instruction, respectively, at some point are electrically combined. And in those bits where opposite values 0 and 1 are combined, a certain average potential appears, conditional 0.5. And then, these values are written back to the F register, and depending on the threshold of the transistor gates, these conditional 0.5 can turn into both 0 and 1. [https://zx-pk.ru/threads/35936-zagadka-plavayushchikh-flagov-scf-ccf-raskryta!.html Source (RU)]
|-
| IR (Instruction Register) || 8-bit || Holds the opcode of the currently executing instruction || Internally used, not accessible by the programmer. Not to be confused with I (Interrupt Vector) and R (Memory Refresh) registers.
