The CPC timings of some instructions will be altered if an interrupt happens. The interrupt test occurs on the last T-State of the instruction, and if it's low, the Z80 will insert 2 wait states to acknowledge the interrupt.
Instructions So, instructions which end in the third or fourth T-State relative to the read alignment for the next instruction fetch will be delayed by an extra 4 T-States. The few instructions which end in the first or second T-State won't since the first instruction fetch/read in the interrupt won't be delayed an extra 4 T-States. [https://www.cpcwiki.eu/forum/programming/interrupt-wait/ Source]
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