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Instructions LD (IX+d),r and LD (IX+d),n surprisingly take 5 and 6 NOPs respectively, even though they are both listed as 19 (4,4,3,5,3) cycles in the datasheet. This happens because LD (IX+d),r has one less Every M-cycle that involves a memory or I/O access operation will be stretched due to do compared to LD (IX+d)bus arbitration. But beware,n as it does not have to fetch its operand from some M-cycles are purely internal and don't involve a memoryor I/O access.

Nevertheless, a few CPC timings can appear surprising at first glance: * Instructions LD (IX+d),r and LD (IX+d),n take 5 and 6 NOPs respectively, even though they are both listed as 19 (4,4,3,5,3) cycles in the datasheet. This happens because LD (IX+d),r has one less memory access operation to do compared to LD (IX+d),n as it does not have to fetch its operand from memory. * Instructions IN r,(C) and OUT (C),r surprisingly take 4 NOPs with CPC timings, even though they are listed as 12 (4,4,4) cycles in the datasheet. This happens because I/O access is not aligned with memory access. On Zilog manual, it is precised that one wait-state TW is automatically inserted after T2 on I/O access.