This is why the EOR instruction effectively takes only 2 cycles.
To be fairHowever, this concept of pipelining only makes sense when we consider looking at full-cycles. If we break it down further into half-cycles, there’s there's no real actual overlap or shortcut happening. ItIn fact, it's the other way around. If the previous instruction ends with a memory write, the CPU must pause has to wait for a half-cycle before fetching the next instruction on the next ϕ2 half-cycle.
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