Changes

To be fair, this concept of pipelining only makes sense when we consider full-cycles. With If we break it down further into half-cycles in mind, there is there’s no real overlap or shortcut happening. It's the other way around. The If the previous instruction ends with a memory write, the CPU has to be idle must pause for 1 a half-cycle when before fetching the preceding next instruction finished with a write access to memory on ϕ2 so that it can fetch the next opcode on next ϕ2 half-cycle.