Changes

Instructions IN r,LD (CIX+d) ,r and OUT LD (CIX+d),r n surprisingly take 4 5 and 6 NOPs with CPC timingsrespectively, even though they are both listed as 12 19 (4,4,43,5,3) cycles in the datasheet. This happens because I/O access is not aligned with LD (IX+d),r has one less memory access. On Zilog manualoperation to do compared to LD (IX+d), n as it is precised that one wait-state TW is automatically inserted after T2 on I/O accessdoes not have to fetch the operand from memory.

On Instructions IN r,(C) and OUT (C),r surprisingly take 4 NOPs with CPCtimings, bus arbitration is done on every CPU bus access. On MSXeven though they are listed as 12 (4, bus arbitration only applies to M1 machine 4,4) cycles but in the datasheet. This happens because I/O access is not aligned with memory access to VRAM has other limitations. On ZX SpectrumZilog manual, bus arbitration it is done not by using the precised that one wait-state TW is automatically inserted after T2 on I/WAIT pin but by disabling the CPU clock when neededO access.