Changes
/* Aleste COLDAT eprom (Gate Array Parameters and Upper ROM Bank) */
== Aleste COLDAT eprom (Gate Array Parameters and Upper ROM Bank) ==
A0..A7 Databus D0..D7
A8 CPU A13
A9 CPU A15
A10 MAPMOD ;affects ONLY the palette bits in COLDAT
D0..D5 XD0..XD5
D6 Not used (not connected)
D7 VRAMACC
COLDAT Addr CPU Addr Content
0000..00FF: 5FFFh ? (filled with incrementing values: 00h..FFh)
0200..02FF: DFFFh Upper ROM Bank
0300..03FF: FFFFh ? (filled with incrementing values: 00h..FFh)
0400..04FF: 5FFFh ? (filled with incrementing values: 00h..FFh)
0500..053F: 7FFFh Gate Array 0 (palette index) (same as MAPMODE=0)