Changes
/* Aleste COLDAT eprom (Gate Array Parameters and Upper ROM Bank) */
== Aleste COLDAT eprom (Gate Array Parameters and Upper ROM Bank) ==
'''Inputs:'''
A0..A7 Databus D0..D7
A8 CPU A13
A9 CPU A15
A10 MAPMOD ;affects ONLY the palette bits in COLDAT
'''Outputs: (enabled only when /IORQ=Low)'''
D0..D5 XD0..XD5
D6 Not used (not connected)
D7 VRAMACC
'''Part A (when MAPMOD=0)''' COLDAT Addr CPU Addr Content 0000..00FF: 5FFFh ? (filled with incrementing values: 00h..FFh) 0100..013F: 7FFFh Gate Array 0 (palette index) 0140..017F: 7FFFh Gate Array 1 (palette data) 0180..01BF: 7FFFh Gate Array 2 (vmode, rom, leds) 01C0..01FF: 7FFFh Gate Array 3 (rambank, etc.) 0200..02FF: DFFFh Upper ROM Bank 0300..03FF: FFFFh ? (filled with incrementing values: 00h..FFh) '''Part B (when MAPMOD=1)''' 0400..04FF: 5FFFh ? (filled with incrementing values: 00h..FFh) 0500..053F: 7FFFh Gate Array 0 (palette index) (same as MAPMODE=0) 0540..057F: 7FFFh Gate Array 1 (palette data) (other than MAPMODE=0) 0580..05BF: 7FFFh Gate Array 2 (vmode, rom, leds) (same as MAPMODE=0) 05C0..05FF: 7FFFh Gate Array 3 (rambank, etc.) (same as MAPMODE=0) 0600..06FF: DFFFh Upper ROM Bank (same as MAPMODE=0) 0700..07FF: FFFFh ? (filled with incrementing values: 00h..FFh)
Address 7FFFh: Gate Array 0: (A13=1, A15=0, DataIn=00h..3Fh) palette index
