Changes
However, this will not be accurate enough:
At the best, VSYNC will become active exactly when PPI port B is read (on the final execution cycle of the "in a,(c)" instruction), and at the program-counter defined by the "continue" label, we will then be synchronised to 4 cycles (the time for "rra" and "jp" instructions) from the start of the VSYNC signal.
At the worst, we will just miss seeing the VSYNC become active the first time PPI port B is read (since it would become active just after "in a,(c)" has executed), and then it will be another 7 cycles (time for "rra", "jp nc" and all but the last execution cycle of "in a,(c)"), before the VSYNC is detected. Then when we get to the program-counter defined by "continue" label, we will then be synchronised to 11 cycles from the start of the VSYNC signal.
Therefore the timing can differ.
