Changes
Z80
,/* Oddities */
* RETI and RETN are identical instructions [https://floooh.github.io/2021/12/17/cycle-stepped-z80.html#the-ei-di-and-retiretn-instructions Source]. The only reason for RETI is so that some other hardware can detect the specific case of returning from the interrupt, by detecting the RETI opcode on the data bus.
* EI has a 1-instruction delay. It is necessary for doing EI/RETI without any danger of nested interrupt routines.
* RST instructions are just a CALL instruction to a fixed address baked in the instruction itself.* Despite what the syntax of the instructions JP (HL/IX/IY) suggests, PC will be loaded with the contents of the register itself, not the indexed value. Those instructions should be understood as JP HL/IX/IY.* IN r,(C) and OUT (C),r instructions syntax is misleading as these instructions actually use the full 16-bit port address contained in BC.* While the syntax of ADD, ADC and SBC instructions all explicitely mention the A register, the SUB instruction does not mention it.* The 16-bit commands ADD HL,ss, ADC HL,ss and SBC HL,ss exist but not the command SUB HL,ss.* NMOS Z80 suffers a problem whereby LD A,I and LD A,R record the state of IFF2 after it has been reset if an interrupt is delivered during that instruction.* The values of F5 and F3 following an SCF or CCF instruction depend on whether the preceding instruction modified the flags or not.* The BIT b,(HL) instruction exposes certain bits of the internal register WZ to the undocumented flags F5 and F3.
* The NOP instruction takes 4 cycles. This is the minimum amount of cycles an instruction can take.
* Instructions IN r,(C) and OUT (C),r surprisingly take 4 NOPs with CPC timings, even though they are listed as 12 (4,4,4) cycles in the datasheet. This happens because I/O access is not aligned with memory access.
