Changes
ASIC
,/* DMA sound channels */
* The argument field (N) of the REPEAT instruction is actually the number of times the loop is taken. The block of code between REPEAT and LOOP instructions is therefore executed N+1 times.
All instructions execute in one cycle, except LOAD which requires at least 8 cycles. An extra cycle is added to a LOAD if the CPU is accessing the PPI, or 2 extra cycles if the CPU access was itself a PSG register write.
The DMA control and status register DCSR (at address 6C0Fh) controls which channels are currently enabled, and also tells the CPU which channel is interrupting:
