Changes
ASIC
,/* Vectored interrupt */
Bits2..1 of the IVR register are unused.
Bit0 of the IVR register controls whether DMA channel interrupts are automatically cleared. Raster interrupts are always automatically cleared regardless of this setting.
Interrupts are prioritized in a fixed sequence. The raster interrupt has the highest priority, followed by DMA channels 2 down to 0 respectively.
