Changes
/* Some bad instruction timing analyses */
CPC timing: 5; quick: 4; low: 4
In fact this instruction does launch two MEM_WR, and shall be prolongated two times.
===== Some bad instruction analyses =====
Based on [[https://cpcrulez.fr/applications_CPM-util-zexall.htm Zexall: Z80 instruction set exerciser]]
====== ED A9 cpd(r) / ED A1 cpi(r) ======
Problem here : CPDR and CPIR has same implementation than CPD and CPI.
=== Alignment of HSYNC Interrupt ===
