Changes
/* TODO : Z80 testbench */
[http://www.winape.net/download/plustest.zip WinAPE plustest.zip (including Instruction and Interrupt timing tests)]
===== Z80 architecture : =========== a) T80.vhdl ======
17 pages of source codes to read.
Contains T80_ALU.vhdl and T80_MCode.vhdl components.
===== Z80 architecture : = b) T80_ALU.vhdl ======
6 pages of source codes to read.
[[http://www.z80.info/decoding.htm § Disassembly tables]] shall make a cool ALU_Op quick reference card, doesn't it ?
===== Z80 architecture : = c) T80_MCode.vhdl ======
First 5 pages, and last 2 pages of source codes to read. Others pages are "always the same" architectually speaking.
Inc_WZ register : take a look at [[http://www.righto.com/2014/10/how-z80s-registers-are-implemented-down.html § The WZ temporary registers]. It's a tmp internal register in fact.
===== Some bad instruction timing analyses =====
Based on [[http://www.winape.net/ WinAPE>download>Plus test>plustest.dsk]] testbench, mapped using [[http://clrhome.org/table/ Z80 instruction set - ClrHome]], instruction described then in [[http://www.zilog.com/docs/z80/um0080.pdf Z80 doc]], against [[http://www.winape.net/ WinAPE] passing testbench timing.
====== 02 LD (BC),A ======
CPC timing: 2; quick: 2; low: 3
Normaly MEM_WR access is not prolongated. This instruction does certainly launch write since first step.
====== 2A LD HL,(nn) ======
CPC timing: 5; quick: 4; low: 4
In fact this instruction does launch two MEM_WR, and shall be prolongated two times.
=== Alignment of HSYNC Interrupt ===
