Difference between revisions of "Schneiderware Summary"

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== Scanned Articles ==
 
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* [[Media:Schneiderware 1 - Intro.pdf|Schneiderware 1 - Intro.pdf]]
 
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* [[Media:Schneiderware 2 - Backplane and Centronics.pdf|Schneiderware 2 - Backplane and Centronics.pdf]]
 
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* [[Media:Schneiderware 3 - Serial V24 Interface.pdf|Schneiderware 3 - Serial V24 Interface.pdf]]
 
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* [[Media:Schneiderware 4 - Power Supply.pdf|Schneiderware 4 - Power Supply.pdf]]
 
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* [[Media:Schneiderware 5 - Real Time Clock.pdf|Schneiderware 5 - Real Time Clock.pdf]]
 
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* [[Media:Schneiderware 6 - Uni-PIO.pdf|Schneiderware 6 - Uni-PIO.pdf]]
 
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* [[Media:Schneiderware 7 - Analog Converter.pdf|Schneiderware 7 - Analog Converter.pdf]]
 
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* [[Media:Schneiderware 8 - Pseudo ROM.pdf|Schneiderware 8 - Pseudo ROM.pdf]]
 
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* [[Media:Schneiderware 9 - Eprommer.pdf|Schneiderware 9 - Eprommer.pdf]]
 
  
 
== Schematics ==
 
== Schematics ==
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<gallery>
 
<gallery>
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File:Schneiderware 2 Basisplatine (component side).jpg |Schneiderware #2<br>Basisplatine (component side)
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File:Schneiderware 2 Basisplatine (component side).jpg |Schneiderware #2a<br>Basisplatine (component side)
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File:Schneiderware 2 Basisplatine (solder side).jpg    |Schneiderware #2<br>Basisplatine (solder side)
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File:Schneiderware 2 Basisplatine (solder side).jpg    |Schneiderware #2a<br>Basisplatine (solder side)
−
File:Schneiderware 2 Centronics (component side).jpg  |Schneiderware #2<br>Centronics (component side)
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File:Schneiderware 2 Centronics (component side).jpg  |Schneiderware #2b<br>Centronics (component side)
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File:Schneiderware 2 Centronics (solder side).jpg      |Schneiderware #2<br>Centronics (solder side)
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File:Schneiderware 2 Centronics (solder side).jpg      |Schneiderware #2b<br>Centronics (solder side)
 
File:Schneiderware 3 V24 (component side).jpg          |Schneiderware #3<br>V24 (component side)
 
File:Schneiderware 3 V24 (component side).jpg          |Schneiderware #3<br>V24 (component side)
 
File:Schneiderware 3 V24 (solder side).jpg            |Schneiderware #3<br>V24 (solder side)
 
File:Schneiderware 3 V24 (solder side).jpg            |Schneiderware #3<br>V24 (solder side)
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File:Schneiderware 6 Uni-PIO (solder side).jpg        |Schneiderware #6<br>Uni-PIO (solder side)
 
File:Schneiderware 6 Uni-PIO (solder side).jpg        |Schneiderware #6<br>Uni-PIO (solder side)
 
</gallery>
 
</gallery>
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== Scanned Articles ==
 +
 +
* [[Media:Schneiderware 1 - Intro.pdf|Schneiderware 1 - Intro.pdf]] - Theory - '''6/1986 page 62-67''', plus preface from 5/1986 page 21, final notes from 11/1987 page 97-99
 +
* [[Media:Schneiderware 2 - Backplane and Centronics.pdf|Schneiderware 2 - Backplane and Centronics.pdf]] - Basisplatine and Printer Port - '''7/1986 page 60-67''', plus complaints from 10/1986 page 10, port B redefined on 12/1986 page 124 and 3/1987 page 8-9, final notes from 11/1987 page 98
 +
* [[Media:Schneiderware 3 - Serial V24 Interface.pdf|Schneiderware 3 - Serial V24 Interface.pdf]] - RS232 Interface - '''8/1986 page 70-77''', plus correction from 9/1986 page 80, final notes from 11/1987 page 98
 +
* [[Media:Schneiderware 4 - Power Supply.pdf|Schneiderware 4 - Power Supply.pdf]] - Netzteil - '''9/1986 page 78-83''', corrections on 10/1986 page 85, 5/1987 page 12
 +
* [[Media:Schneiderware 5 - Real Time Clock.pdf|Schneiderware 5 - Real Time Clock.pdf]] - Echtzeituhr - '''10/1986 page 78-85''', corrections on 12/1986 page 6 and 3/1987 page 9, 9/1987 page 9, ROM driver in 4/1987 page 29, final notes from 11/1987 page 98-99
 +
* [[Media:Schneiderware 6 - Uni-PIO.pdf|Schneiderware 6 - Uni-PIO.pdf]] - 48 I/O lines - '''12/1986 page 124-130''', advert on 1/1987 page 144, correction on 5/1987 page 12, final notes from 11/1987 page 99
 +
* [[Media:Schneiderware 7 - Analog Converter.pdf|Schneiderware 7 - Analog Converter.pdf]] - 8 analog inputs, 2 analog outputs - '''3/1987 page 32-45''', final notes from 11/1987 page 99
 +
* [[Media:Schneiderware 8 - Pseudo ROM.pdf|Schneiderware 8 - Pseudo ROM.pdf]] - SRAM and EPROM mapped as ROM - '''4/1987 page 26-34''', plus corrections in 5/1987 page 32-34
 +
* [[Media:Schneiderware 9 - Eprommer.pdf|Schneiderware 9 - Eprommer.pdf]] - EPROM Burner - '''6/1987 page 122-131'''
  
 
== Software ==
 
== Software ==
  
−
Databoxes: '''UHR8000''' RTC-RAM-driver in 10-1986 (hex listing, plus [[Hisoft Devpac]] source code) (caution this version uses incorrect I/O addresses FBE1-FBE3), '''UHRC000X''' RTC-ROM-driver in 4-1987 (this version uses correct I/O addresses FBE2-FBE4). Uni-PIO examples in 12-1986 (=only a few basic lines). There seem to be no Centronics and V/24 drivers included in databoxes.
+
Databoxes: '''UHR8000''' RTC-RAM-driver in 10-1986 (hex listing, plus [[Hisoft Devpac]] source code) (caution this version uses incorrect I/O addresses FBE1-FBE3), '''UHRC000X''' RTC-ROM-driver in 4-1987 (this version uses correct I/O addresses FBE2-FBE4). Uni-PIO examples in 12-1986 (=only a few basic lines). There seem to be no Centronics and V.24 drivers included in databoxes.
  
 
== Datasheets ==
 
== Datasheets ==
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Info on various ECB Bus variants can be found here: [[ECB Bus]].
 
Info on various ECB Bus variants can be found here: [[ECB Bus]].
 +
 +
[[Category: Peripherals]]

Latest revision as of 06:04, 9 April 2015

This page contains a summary of Schneiderware related info. For details refer to the separate pages (links are found on the Schneiderware page.

I/O Port Summary

Address (default) Address (alternate) Usage
DFxxh N/A Schneiderware RAM/EPROM - Expansion ROM bank number (W)
Battery-backed SRAM and/or EPROM are selected when the bank-number matches the jumper-selected values; the memory is then mapped to C000h..FFFFh (in case of READing one must also enable upper ROM via Gate Array). The bank number decoding is a bit strange:
  • EPROM/Read bank: All 8 bits decoded (bank 00h..FFh)
  • SRAM/Read bank: Only lower 4 bits decoded (bank X0h..XFh)
  • SRAM/Write bank: Only lower 4 bits decoded (bank X0h..XFh)

The SRAM/Write mode doesn't disable the internal RAM in the CPC, so writes are going both to SRAM and normal RAM at C000-FFFF, that no matter if upper ROM is enabled/disabled via Gate Array; the author recommended to map VRAM to 4000-7FFF via CRTC registers, in order to prevent video dirt during writing.

F8E0h F8F0h (later redefined to F8E4h) Schneiderware Centronics Port 8255 PPI Port A (data)
F8E1h F8F1h (later redefined to F8E5h) Schneiderware Centronics Port 8255 PPI Port B (unused)
F8E2h F8F2h (later redefined to F8E6h) Schneiderware Centronics Port 8255 PPI Port C (busy/strobe)
(bit7=busy, bit6-1=unused, bit0=strobe; strobe is externally inverted)
(autolf is wired to GND, all other control/status signals are not connected)
F8E3h F8F3h (later redefined to F8E7h) Schneiderware Centronics Port 8255 PPI Control
F8E8h F8F0h, F8F8h Schneiderware Uni-PIO 8255 PPI #1 Port A (without pull-ups, with red LEDs)
F8E9h F8F1h, F8F9h Schneiderware Uni-PIO 8255 PPI #1 Port B (with pull-ups and green LEDs)
F8EAh F8F2h, F8FAh Schneiderware Uni-PIO 8255 PPI #1 Port C (lower 4bit without pull-ups and red LEDs, upper 4bit with pull-ups and green LEDs)
F8EBh F8F3h, F8FBh Schneiderware Uni-PIO 8255 PPI #1 Control
F8ECh F8F4h, F8FCh Schneiderware Uni-PIO 8255 PPI #2 Port A (without pull-ups or LEDs)
F8EDh F8F5h, F8FDh Schneiderware Uni-PIO 8255 PPI #2 Port B (without pull-ups or LEDs)
F8EEh F8F6h, F8FEh Schneiderware Uni-PIO 8255 PPI #2 Port C (without pull-ups or LEDs)
F8EFh F8F7h, F8FFh Schneiderware Uni-PIO 8255 PPI #2 Control
F9E0h F9E2h Schneiderware V/24 Interface 8251 USART Data
F9E1h F9E3h Schneiderware V/24 Interface 8251 USART Control
F9ECh F9E8h Schneiderware V/24 Interface 8253 Timer 0 (TX clock)
F9EDh F9E9h Schneiderware V/24 Interface 8253 Timer 1 (RX clock)
F9EEh F9EAh Schneiderware V/24 Interface 8253 Timer 2 (unused)
F9EFh F9EBh Schneiderware V/24 Interface 8253 Timer Control
Note: Timer clock input is jumper select-able: 2MHz (default), or 1MHz
FAE0h N/A Schneiderware Analog Converter ADC 0848 A/D Converter (R/W)
Read: Get 8bit data from selected channel
Write: Select channel & mode; bit0..2=channel (0..7), bit3..4=mode, bit5-7=unused
  • Mode 0 (or 1) - Differential: Plus=Channel(N), Minus=Channel(N XOR 1)
  • Mode 2 - Single-Ended: Plus=Channel(N) and Minus=AGND
  • Mode 3 - Pseudo-Differential: Plus=Channel(N) and Minus=Channel(7)
FAE1h N/A Schneiderware Analog Converter DAC 0832 D/A Converter #1 (W)
Write: 8bit data
FAE2h N/A Schneiderware Analog Converter DAC 0832 D/A Converter #2 (W)
Write: 8bit data
FAF0h N/A Schneiderware EPROM Burner 8255 PPI #1 Port A (Data, 8bit)
FAF1h N/A Schneiderware EPROM Burner 8255 PPI #1 Port B (Address LSBs, 8bit)
FAF2h N/A Schneiderware EPROM Burner 8255 PPI #1 Port C (Address MSBs, 7bit; bit7=unused)
FAF3h N/A Schneiderware EPROM Burner 8255 PPI #1 Control
FAF4h N/A Schneiderware EPROM Burner 8255 PPI #2 Port A (bit0-7=unused)
FAF5h N/A Schneiderware EPROM Burner 8255 PPI #2 Port B (bit0-5=unused, bit6=Red LED, bit7=Green LED)
FAF6h N/A Schneiderware EPROM Burner 8255 PPI #2 Port C (programming signals, 8bit)
FAF7h N/A Schneiderware EPROM Burner 8255 PPI #2 Control
FBE2h BUGGED:FBE1h Schneiderware Real Time Clock Index/Control (W)
FBE3h BUGGED:FBE2h Schneiderware Real Time Clock Data 4bit (W)
FBE4h BUGGED:FBE3h Schneiderware Real Time Clock Data 4bit (R)

Schematics

  • Motherboard

  • Centronics

  • Uni-PIO

  • RS232

  • Power Supply

  • DAC/ADC

  • RTC

  • SRAM/EPROM

  • Eprom Burner

Pictures

  • Schneiderware #2a
    Basisplatine (component side)

  • Schneiderware #2a
    Basisplatine (solder side)

  • Schneiderware #2b
    Centronics (component side)

  • Schneiderware #2b
    Centronics (solder side)

  • Schneiderware #3
    V24 (component side)

  • Schneiderware #3
    V24 (solder side)

  • Schneiderware #4
    Supply/Netzteil (only +12V/-12V components installed)

  • Schneiderware #4
    Supply/Netzteil (solder side)

  • Schneiderware #5
    RTC/Echtzeituhr (component side)

  • Schneiderware #5
    RTC/Echtzeituhr (solder side)

  • Schneiderware #6
    Uni-PIO (component side)

  • Schneiderware #6
    Uni-PIO (solder side)

Scanned Articles

Software

Databoxes: UHR8000 RTC-RAM-driver in 10-1986 (hex listing, plus Hisoft Devpac source code) (caution this version uses incorrect I/O addresses FBE1-FBE3), UHRC000X RTC-ROM-driver in 4-1987 (this version uses correct I/O addresses FBE2-FBE4). Uni-PIO examples in 12-1986 (=only a few basic lines). There seem to be no Centronics and V.24 drivers included in databoxes.

Datasheets

Info on various ECB Bus variants can be found here: ECB Bus.

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