Difference between revisions of "PAL16L8"

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(ASIC compatibility)
 
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The CPC6128 second bank of 64K RAM is controlled by a PAL 16L8 chip. It has the Amstrad part number 40031.
+
Programmable Array Logic (PAL). Not to be confused with PAL, the colour encoding system for analog televisions.
 +
 
 +
The CPC6128 second page of 64KB RAM is controlled by a PAL chip.
  
 
On the CPC 6128 schematic, it is top centre: [http://www.cpcwiki.eu/imgs/4/4a/CPC6128_Schematic.png CPC6128 Schematic] however the X inputs aren't distinguished.
 
On the CPC 6128 schematic, it is top centre: [http://www.cpcwiki.eu/imgs/4/4a/CPC6128_Schematic.png CPC6128 Schematic] however the X inputs aren't distinguished.
 +
 +
<br>
 +
 +
== IC Models used in CPC ==
 +
These are the ones known to be used in the CPC by looking at pictures of CPC mainboards:
 +
 +
* HAL16L8ACN [https://www.cpcwiki.eu/imgs/6/67/CPC6128_PCB_Top_%28Z70290_MC0020F%29.jpg Source]
 +
* PAL16L8ACN [https://www.cpcwiki.eu/imgs/4/4e/CPC6128_PCB_Top_%28Z70290_MC0020G%29.jpg Source]
 +
 +
They both wear the same Amstrad part number 40031. On the Amstrad chassis schematic diagram, this part is numbered 40030. [https://www.cpcwiki.eu/imgs/4/4a/CPC6128_Schematic.png Source]
  
 
<br>
 
<br>
  
 
== PAL MMR register ==
 
== PAL MMR register ==
This register controls how the extended RAM is banked into the CPU address space. It doesn't affect the video display at all as the Gate Array can only access the Base 64k page of RAM.
+
This register controls how the extended RAM is banked into the CPU address space. It doesn't affect the video display at all as the [[Gate Array]] can only access the Base 64k page of RAM.
  
{|{{Prettytable|width: 700px; font-size: 2em;}}
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{| class="wikitable"
|colspan=2|'''MMR'''||colspan=3|'''64K page'''||'''S'''||colspan=2|'''MM'''||colspan=4 style="text-align: center;"|'''CPU Memory Mapping'''
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!colspan=2|MMR
 +
!colspan=3|64K page
 +
!S
 +
!colspan=2|MM
 +
!colspan=4|CPU Memory Mapping
 
|-
 
|-
|'''7'''
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!7
|'''6'''
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!6
|'''5'''
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!5
|'''4'''
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!4
|'''3'''
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!3
|'''2'''
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!2
|'''1'''
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!1
|'''0'''
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!0
|style="text-align: center;"|'''&0000-&3fff'''
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!&0000-&3fff
|style="text-align: center;"|'''&4000-&7fff'''
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!&4000-&7fff
|style="text-align: center;"|'''&8000-&bfff'''
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!&8000-&bfff
|style="text-align: center;"|'''&c000-&ffff'''
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!&c000-&ffff
 
|-
 
|-
 
|1
 
|1
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== PAL I/O port ==
 
== PAL I/O port ==
  
Note that no settings are stored in the Gate Array itself regarding register 3 (MMR). But the PAL and Gate Array share an I/O port address so that it appears to be the same chip to the programmer.
+
Note that no settings are stored in the Gate Array itself regarding the MMR register. But the PAL and Gate Array share an I/O port address so that it appears to be the same chip to the programmer.
  
 
Bit14 of the PAL selection address can be at 0 or 1 on CPCs equipped with CRTCs 3, 4.  
 
Bit14 of the PAL selection address can be at 0 or 1 on CPCs equipped with CRTCs 3, 4.  
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</pre>
 
</pre>
  
Note: The CPC 464/664 cannot deal with A14/A15 for Base 64k page like the 6128 does. So external RAM expansions differ in their behaviour regarding &C3 mode. See [https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/464-preasic-c3-ram-configuration-and-rom-7/ Discussion on the forum] and [https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/dk%27tronics-ram-c3-selection-464/ Another discussion]
+
Note: The CPC 464/664 cannot deal with A14/A15 for Base 64k page like the 6128 does. So external RAM expansions can differ in their behaviour regarding &C3 mode. See [https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/464-preasic-c3-ram-configuration-and-rom-7/ Discussion on the forum] and [https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/dk%27tronics-ram-c3-selection-464/ Another discussion]
 +
 
 +
<br>
 +
 
 +
== ASIC compatibility ==
 +
 
 +
Most existing RAM expansions except Gemini have a problem. [https://pulkomandy.github.io/shinra.github.io/gemini.html Source]
 +
 
 +
The issue is specific to the Amstrad Plus machines which add yet another complication to the memory mapping handling on CPC machines. Basically, the ASIC can be memory mapped and hide a part of the RAM. This works well for the main RAM bank, and on the CPC, it also works for the internal extra 64K of RAM, which can be mapped at the same address. If you try to map both the RAM and the ASIC there, the ASIC is mapped and the RAM is not accessible until the ASIC is moved out of the way.
 +
 
 +
Unfortunately, memory expansions designed for the classic CPC does not take this into account. For some of them, because they were designed before the Amstrad Plus ASIC existed, and for some, the designers didn't think of it or decided it was not important. As a result, these extensions can enter in conflict with the ASIC, which will result, at best, in software crashes, and at worst, in '''damage to the hardware'''.
 +
 
 +
Software that is known to hit this problem with existing memory expansions:
 +
 
 +
*[https://www.cpc-power.com/index.php?page=detail&num=14940 CRTC3 demo]
 +
*[https://soundtrackerdma.cpcscene.net/doku.php?id=en:download Soundtracker DMA]
  
 
<br>
 
<br>
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<br>
 
<br>
  
== See also ==
+
== Internal PAL on CPC 6128 ==
 +
 
 +
[[File:Amstrad.cpc6128.pal.ga.jpg]]
 +
 
 +
<br>
 +
 
 +
== Related pages ==
  
 
*[[Gate Array and ASIC Pin-Outs]]
 
*[[Gate Array and ASIC Pin-Outs]]

Latest revision as of 10:06, 23 October 2024

Programmable Array Logic (PAL). Not to be confused with PAL, the colour encoding system for analog televisions.

The CPC6128 second page of 64KB RAM is controlled by a PAL chip.

On the CPC 6128 schematic, it is top centre: CPC6128 Schematic however the X inputs aren't distinguished.


IC Models used in CPC

These are the ones known to be used in the CPC by looking at pictures of CPC mainboards:

They both wear the same Amstrad part number 40031. On the Amstrad chassis schematic diagram, this part is numbered 40030. Source


PAL MMR register

This register controls how the extended RAM is banked into the CPU address space. It doesn't affect the video display at all as the Gate Array can only access the Base 64k page of RAM.

MMR 64K page S MM CPU Memory Mapping
7 6 5 4 3 2 1 0 &0000-&3fff &4000-&7fff &8000-&bfff &c000-&ffff
1 1 x 0 0 0 Base 64k / Bank 0 Base 64k / Bank 1 Base 64k / Bank 2 Base 64k / Bank 3
1 1 p 0 0 1 Base 64k / Bank 0 Base 64k / Bank 1 Base 64k / Bank 2 Page p / Bank 3
1 1 p 0 1 0 Page p / Bank 0 Page p / Bank 1 Page p / Bank 2 Page p / Bank 3
1 1 p 0 1 1 Base 64k / Bank 0 Base 64k / Bank 3 Base 64k / Bank 2 Page p / Bank 3
1 1 p 1 b Base 64k / Bank 0 Page p / Bank b Base 64k / Bank 2 Base 64k / Bank 3

On a standard 128k machine (unexpanded), bits5..3 are ignored. Page will always be fixed to Page 0.


PAL I/O port

Note that no settings are stored in the Gate Array itself regarding the MMR register. But the PAL and Gate Array share an I/O port address so that it appears to be the same chip to the programmer.

Bit14 of the PAL selection address can be at 0 or 1 on CPCs equipped with CRTCs 3, 4. It must be at 1 on CRTCs 0, 1 and 2 (The result is not guaranteed).

For compatibility reasons, it is strongly advised to always set bit14 to 1 to select PAL.

Furthermore, if bit14=0 then CRTC will be selected too.


PAL Type Detection

10 OUT &7F00,&C0:POKE &4000,&C0
20 OUT &7F00,&C7:POKE &4000,&C7:OUT &7F00,&C0
30 IF PEEK(&4000)=&C7 THEN PRINT"PAL chip absent/inactive":END
40 OUT &3FFF,&C7
50 IF PEEK(&4000)=&C7 THEN PRINT"IO Bit14=0 PAL selected" ELSE PRINT"IO Bit14=0 PAL not selected"
60 OUT &7F00,&C0:POKE &C000,&C0
70 OUT &7F00,&C3:POKE &4000,&C3:OUT &7F00,&C0
80 IF PEEK(&C000)=&C3 THEN PRINT"Valid RAM mode &C3" ELSE PRINT"Invalid RAM mode &C3"

Note: The CPC 464/664 cannot deal with A14/A15 for Base 64k page like the 6128 does. So external RAM expansions can differ in their behaviour regarding &C3 mode. See Discussion on the forum and Another discussion


ASIC compatibility

Most existing RAM expansions except Gemini have a problem. Source

The issue is specific to the Amstrad Plus machines which add yet another complication to the memory mapping handling on CPC machines. Basically, the ASIC can be memory mapped and hide a part of the RAM. This works well for the main RAM bank, and on the CPC, it also works for the internal extra 64K of RAM, which can be mapped at the same address. If you try to map both the RAM and the ASIC there, the ASIC is mapped and the RAM is not accessible until the ASIC is moved out of the way.

Unfortunately, memory expansions designed for the classic CPC does not take this into account. For some of them, because they were designed before the Amstrad Plus ASIC existed, and for some, the designers didn't think of it or decided it was not important. As a result, these extensions can enter in conflict with the ASIC, which will result, at best, in software crashes, and at worst, in damage to the hardware.

Software that is known to hit this problem with existing memory expansions:


Initial replacement equation (Porchy)

The following equations were worked out by Porchy (member on CPCWiki Forum). These can be used to program replacements:

A15OUT = (!X2 & !X1 & A14
     # !X3 & !X2 & A14
     # A15); 

!X1 = (!A15 & D7ANDD6 & RESET & !IOWR & D0
     # !X1 & RESET & IOWR
     # !X1 & !D7ANDD6 & RESET
     # !X1 & A15 & RESET);

!X2 = (!A15 & D7ANDD6 & RESET & !IOWR & D1
     # !X2 & RESET & IOWR
     # !X2 & !D7ANDD6 & RESET
     # !X2 & A15 & RESET);

!X3 = (!A15 & D7ANDD6 & RESET & !IOWR & D2
     # !X3 & RESET & IOWR
     # !X3 & !D7ANDD6 & RESET
     # !X3 & A15 & RESET);

!CAS1 = (X3 & !X1 & A15 & A14 & !NCAS & !RAMDIS & !CPU & CAS0
     # !X3 & !A15 & A14 & !NCAS & !RAMDIS & !CPU & CAS0
     # X3 & !X2 & X1 & !NCAS & !RAMDIS & !CPU & CAS0
     # !NCAS & CAS0 & !CAS1);

!CAS0 = (X3 & X2 & X1 & !NCAS & !RAMDIS & CAS1
     # X3 & !X1 & !A15 & !NCAS & !RAMDIS & CAS1
     # !X3 & A15 & !NCAS & !RAMDIS & CAS1
     # !X1 & !A14 & !NCAS & !RAMDIS & CAS1
     # !X3 & !A14 & !NCAS & !RAMDIS & CAS1
     # !NCAS & !RAMDIS & CPU & CAS1
     # !NCAS & !CAS0 & CAS1);

A14OUT = (A15 & A14
     # !X1 & A14
     # X3 & A14);

File:Amstrad6128.jed Original JED File posted on CPCWiki Forum


Fixed version (Gerald)

Original version from Porchy suffer from a bad handling of the RAMDIS signal. This cause screen artefact when accessing an external extension RAM like XMEM.

A14OUT     = !(  !A14
             #   !A15 & !Q0 & Q2 );

A15OUT     = !(  !A15 & !A14
             #   !A15 & !Q1
             #   !A15 & !Q0 & !Q2 );

Q0     = (  D7ANDD6 & nRESET & D0 & !A15 & !nIOWR
         #   !D7ANDD6 & nRESET & Q0
         #   nRESET & A15 & Q0
         #   nRESET & nIOWR & Q0 );

Q1     = (  D7ANDD6 & nRESET & D1 & !A15 & !nIOWR
         #   !D7ANDD6 & nRESET & Q1
         #   nRESET & A15 & Q1
         #   nRESET & nIOWR & Q1 );

Q2     = (  D7ANDD6 & nRESET & D2 & !A15 & !nIOWR
         #   !D7ANDD6 & nRESET & Q2
         #   nRESET & A15 & Q2
         #   nRESET & nIOWR & Q2 );

nCAS0     = (  nCAS
            #   RAMDIS & !nCPU & nCAS0
            #   !A15 & A14 & !nCPU & Q2 & nCAS0
            #   A15 & A14 & !nCPU & Q0 & !Q2 & nCAS0
            #   !nCPU & !Q0 & Q1 & !Q2 & nCAS0
            #   !nCAS1 );

nCAS1     = !(  !RAMDIS & !nCAS & !A15 & A14 & !nCPU & Q2 & nCAS0
            #   !RAMDIS & !nCAS & A15 & A14 & !nCPU & Q0 & !Q2 & nCAS0
            #   !RAMDIS & !nCAS & !nCPU & !Q0 & Q1 & !Q2 & nCAS0
            #   !nCAS & !A15 & A14 & Q2 & nCAS0 & !nCAS1
            #   !nCAS & A15 & A14 & Q0 & !Q2 & nCAS0 & !nCAS1
            #   !nCAS & !Q0 & Q1 & !Q2 & nCAS0 & !nCAS1 );

File:CPC6128.JED : Fixed version of Amstrad 40031 GAL replacement

File:CPC6128.hex : Fixed version of Amstrad 40031 GAL replacement, Hex Intel version.


Internal PAL on CPC 6128

Amstrad.cpc6128.pal.ga.jpg


Related pages