Changes
/* DRAM refresh */
== DRAM refresh ==
On Amstrad CPC, the Gate Array is responsible for the DRAM refresh , instead of using the Z80 built-in DRAM refresh mechanism. The reason is that there can only be 3 DRAM accesses per microsecond on this architecture.
The Z80 generates a maximum of one request per microsecond. The CPC also requires two memory accesses per microsecond for reading video data.
