Changes
/* DRAM refresh */
The Z80 generates a maximum of one request per microsecond. The CPC also requires two memory accesses per microsecond for reading video data.
The CPC specs 4164-20 DRAMs. These require 330nS for a read or write cycle. The CPC also uses the optimised sequential CAS cycles to read the two video data bytesin half a microsecond. [https://www.cpcwiki.eu/forum/amstrad-cpc-hardware/the-cpc-revision-zero-article/msg243769/ Source]
The way to cause the RAM refresh to fail in both a Plus or normal CPC is simply to stop a few bits of the CRTC address changing (ie. never refresh the selected area).
