Changes
Z80
,/* Oddities */
* The BIT b,(HL) instruction exposes certain bits of the internal register WZ to the undocumented flags F5 and F3.
* The NOP instruction takes 4 cycles. This is the minimum amount of cycles an instruction can take.
* Instructions IN r,(C) and OUT (C),r surprisingly take 4 NOPs with CPC timings, even though they are listed as 12 (4,4,4) cycles in the datasheet. This happens because I/O access is not aligned with memory access. On Zilog manual, it is precised that one wait-state TW is automatically inserted after T2 on I/O access.
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