Difference between revisions of "Default I/O Port Summary"

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This list shows only the internal standard I/O ports, as used in the BIOS ROM of the CPC 464/664/6128 BIOS, and in the AMSDOS ROM of the CPC 664/6128 and DDI-1. For a more complete list, including all Peripherals, see the [[I/O Port Summary|Complete I/O Port Summary]].
 
This list shows only the internal standard I/O ports, as used in the BIOS ROM of the CPC 464/664/6128 BIOS, and in the AMSDOS ROM of the CPC 664/6128 and DDI-1. For a more complete list, including all Peripherals, see the [[I/O Port Summary|Complete I/O Port Summary]].
  
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{|{{Prettytable|width: 700px; font-size: 2em;}}
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<br>
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|'''I/O'''||'''Decoded as'''||'''Port'''||'''Read'''||'''Write'''
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 +
== I/O Ports ==
 +
 
 +
{| class="wikitable"
 +
!I/O
 +
!Decoded as
 +
!Port
 +
!Read
 +
!Write
 
|-
 
|-
 
|#7FXX||%01xxxxxx xxxxxxxx||[[Gate Array]]||-||Write
 
|#7FXX||%01xxxxxx xxxxxxxx||[[Gate Array]]||-||Write
 
|-
 
|-
−
|#7FXX||%0xxxxxxx xxxxxxxx||PAL extension to [[Gate Array]] for 128K RAM banking||-||Write
+
|#7FXX||%0xxxxxxx xxxxxxxx||[[PAL16L8|PAL]] extension to [[Gate Array]] for 128K RAM banking||-||Write
 
|-
 
|-
 
|#BCXX||%x0xxxx00 xxxxxxxx||6845 [[CRTC]] Index|| - ||Write
 
|#BCXX||%x0xxxx00 xxxxxxxx||6845 [[CRTC]] Index|| - ||Write
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|#EFXX||%xxx0xxxx xxxxxxxx||[[Printer Port]]|| - ||Write
 
|#EFXX||%xxx0xxxx xxxxxxxx||[[Printer Port]]|| - ||Write
 
|-
 
|-
−
|#F4XX||%xxxx0x00 xxxxxxxx||[[8255]] PIO Port A ([[PSG]] Data)||Read||Write
+
|#F4XX||%xxxx0x00 xxxxxxxx||[[8255]] PPI Port A ([[PSG]] Data)||Read||Write
 
|-
 
|-
−
|#F5XX||%xxxx0x01 xxxxxxxx||[[8255]] PIO Port B (Vsync,[[Printer Port|PrnBusy]],Tape,etc.)||Read|| -  
+
|#F5XX||%xxxx0x01 xxxxxxxx||[[8255]] PPI Port B (Vsync,[[Printer Port|PrnBusy]],Tape,etc.)||Read|| -  
 
|-
 
|-
−
|#F6XX||%xxxx0x10 xxxxxxxx||[[8255]] PIO Port C (KeybRow,Tape,[[PSG]] Control)|| - ||Write
+
|#F6XX||%xxxx0x10 xxxxxxxx||[[8255]] PPI Port C (KeybRow,Tape,[[PSG]] Control)|| - ||Write
 
|-
 
|-
−
|#F7XX||%xxxx0x11 xxxxxxxx||[[8255]] PIO Control-Register|| - ||Write
+
|#F7XX||%xxxx0x11 xxxxxxxx||[[8255]] PPI Control-Register|| - ||Write
 
|-
 
|-
 
|#F8FF||N/A||[[Peripheral Soft Reset]] (MC_BOOT_PROGRAM and MC_START_PROGRAM do OUT [F8FF],FF)|| - ||Write
 
|#F8FF||N/A||[[Peripheral Soft Reset]] (MC_BOOT_PROGRAM and MC_START_PROGRAM do OUT [F8FF],FF)|| - ||Write
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|#FA7E||%xxxxx0x0 0xxxxxxx||Floppy Motor Control (for [[765 FDC]])|| - ||Write
 
|#FA7E||%xxxxx0x0 0xxxxxxx||Floppy Motor Control (for [[765 FDC]])|| - ||Write
 
|-
 
|-
−
|#FADC||?||[[Amstrad Serial Interface]] Z80-SIO / DART port A Data Register||Read||Write
+
|#FADC||%xxxxx0x0 xx0xxx00||[[Amstrad Serial Interface]] Z80-SIO / DART port A Data Register||Read||Write
 
|-
 
|-
−
|#FADD||?||[[Amstrad Serial Interface]] Z80-SIO / DART port A Control Reg.||Read||Write
+
|#FADD||%xxxxx0x0 xx0xxx01||[[Amstrad Serial Interface]] Z80-SIO / DART port A Control Reg.||Read||Write
 
|-
 
|-
−
|#FADE||?||[[Amstrad Serial Interface]] Z80-SIO / DART port B Data Register||Read||Write
+
|#FADE||%xxxxx0x0 xx0xxx10||[[Amstrad Serial Interface]] Z80-SIO / DART port B Data Register||Read||Write
 
|-
 
|-
−
|#FADF||?||[[Amstrad Serial Interface]] Z80-SIO / DART port B Control Reg.||Read||Write
+
|#FADF||%xxxxx0x0 xx0xxx11||[[Amstrad Serial Interface]] Z80-SIO / DART port B Control Reg.||Read||Write
 
|-
 
|-
 
|#FB7E||%xxxxx0x1 0xxxxxx0||[[765 FDC]] (internal) Status Register||Read|| -  
 
|#FB7E||%xxxxx0x1 0xxxxxx0||[[765 FDC]] (internal) Status Register||Read|| -  
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|#FB7F||%xxxxx0x1 0xxxxxx1||[[765 FDC]] (internal) Data Register||Read||Write
 
|#FB7F||%xxxxx0x1 0xxxxxx1||[[765 FDC]] (internal) Data Register||Read||Write
 
|-
 
|-
−
|#FBDC||?||[[Amstrad Serial Interface]] 8253 Timer counter 0||Read||Write
+
|#FBDC||%xxxxx0x1 xx0xxx00||[[Amstrad Serial Interface]] 8253 Timer counter 0||Read||Write
 
|-
 
|-
−
|#FBDD||?||[[Amstrad Serial Interface]] 8253 Timer counter 1||Read||Write
+
|#FBDD||%xxxxx0x1 xx0xxx01||[[Amstrad Serial Interface]] 8253 Timer counter 1||Read||Write
 
|-
 
|-
−
|#FBDE||?||[[Amstrad Serial Interface]] 8253 Timer counter 2||Read||Write
+
|#FBDE||%xxxxx0x1 xx0xxx10||[[Amstrad Serial Interface]] 8253 Timer counter 2||Read||Write
 
|-
 
|-
−
|#FBDF||?||[[Amstrad Serial Interface]] 8253 Timer Modus Select|| - ||Write
+
|#FBDF||%xxxxx0x1 xx0xxx11||[[Amstrad Serial Interface]] 8253 Timer Modus Select|| - ||Write
 
|-
 
|-
 
|}
 
|}
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* The eight [[Amstrad Serial Interface]] ports are pre-defined as shown above in the AMSDOS ROM. However, neither the CPC 664/6128/Plus nor DDI-1 do actually contain the corresponding RS232 hardware.
 
* The eight [[Amstrad Serial Interface]] ports are pre-defined as shown above in the AMSDOS ROM. However, neither the CPC 664/6128/Plus nor DDI-1 do actually contain the corresponding RS232 hardware.
  
−
[[Category:Programming]] [[Category:Stub]][[Category:Built in Hardware]]
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* Bit14 of the PAL selection address must be at 1 on CPCs equipped with CRTCs 0/1/2. It can be at 0 or 1 on CRTCs 3/4. For compatibility reasons, it is strongly advised to always set bit14 to 1 to select PAL.
 +
 
 +
* As components use partial address decoding, it is therefore possible to send the same value to different components '''simultaneously''' by carefully using custom I/O ports.
 +
 
 +
<br>
 +
 
 +
== Memory Mapped I/O Ports ==
 +
 
 +
{| class="wikitable"
 +
!Mem
 +
!Decoded as
 +
!Port
 +
!Read
 +
!Write
 +
|-
 +
|#4000-7FFF||%01xxxxxx xxxxxxxx||ASIC - CPC+/GX4000 registers|| Read || Write
 +
|-
 +
|}
 +
 
 +
See the [[ASIC]] page for details.
 +
 
 +
<br>
 +
 
 +
==Related pages==
 +
 
 +
*[[Arnold V specs]]
 +
*[[Arnold V Specs Revised]]
 +
 
 +
[[Category:Programming]] [[Category:CPC Internal Components]]

Latest revision as of 06:23, 4 September 2024

This list shows only the internal standard I/O ports, as used in the BIOS ROM of the CPC 464/664/6128 BIOS, and in the AMSDOS ROM of the CPC 664/6128 and DDI-1. For a more complete list, including all Peripherals, see the Complete I/O Port Summary.


I/O Ports

I/O Decoded as Port Read Write
#7FXX %01xxxxxx xxxxxxxx Gate Array - Write
#7FXX %0xxxxxxx xxxxxxxx PAL extension to Gate Array for 128K RAM banking - Write
#BCXX %x0xxxx00 xxxxxxxx 6845 CRTC Index - Write
#BDXX %x0xxxx01 xxxxxxxx 6845 CRTC Data Out - Write
#BEXX %x0xxxx10 xxxxxxxx 6845 CRTC Status (as far as supported) Read -
#BFXX %x0xxxx11 xxxxxxxx 6845 CRTC Data In (as far as supported) Read -
#DFXX %xx0xxxxx xxxxxxxx Upper ROM Bank Number - Write
#EFXX %xxx0xxxx xxxxxxxx Printer Port - Write
#F4XX %xxxx0x00 xxxxxxxx 8255 PPI Port A (PSG Data) Read Write
#F5XX %xxxx0x01 xxxxxxxx 8255 PPI Port B (Vsync,PrnBusy,Tape,etc.) Read -
#F6XX %xxxx0x10 xxxxxxxx 8255 PPI Port C (KeybRow,Tape,PSG Control) - Write
#F7XX %xxxx0x11 xxxxxxxx 8255 PPI Control-Register - Write
#F8FF N/A Peripheral Soft Reset (MC_BOOT_PROGRAM and MC_START_PROGRAM do OUT [F8FF],FF) - Write
#FA7E %xxxxx0x0 0xxxxxxx Floppy Motor Control (for 765 FDC) - Write
#FADC %xxxxx0x0 xx0xxx00 Amstrad Serial Interface Z80-SIO / DART port A Data Register Read Write
#FADD %xxxxx0x0 xx0xxx01 Amstrad Serial Interface Z80-SIO / DART port A Control Reg. Read Write
#FADE %xxxxx0x0 xx0xxx10 Amstrad Serial Interface Z80-SIO / DART port B Data Register Read Write
#FADF %xxxxx0x0 xx0xxx11 Amstrad Serial Interface Z80-SIO / DART port B Control Reg. Read Write
#FB7E %xxxxx0x1 0xxxxxx0 765 FDC (internal) Status Register Read -
#FB7F %xxxxx0x1 0xxxxxx1 765 FDC (internal) Data Register Read Write
#FBDC %xxxxx0x1 xx0xxx00 Amstrad Serial Interface 8253 Timer counter 0 Read Write
#FBDD %xxxxx0x1 xx0xxx01 Amstrad Serial Interface 8253 Timer counter 1 Read Write
#FBDE %xxxxx0x1 xx0xxx10 Amstrad Serial Interface 8253 Timer counter 2 Read Write
#FBDF %xxxxx0x1 xx0xxx11 Amstrad Serial Interface 8253 Timer Modus Select - Write
  • The three 765 FDC floppy ports are contained in CPC 664/6128/Plus and DDI-1 only.
  • The eight Amstrad Serial Interface ports are pre-defined as shown above in the AMSDOS ROM. However, neither the CPC 664/6128/Plus nor DDI-1 do actually contain the corresponding RS232 hardware.
  • Bit14 of the PAL selection address must be at 1 on CPCs equipped with CRTCs 0/1/2. It can be at 0 or 1 on CRTCs 3/4. For compatibility reasons, it is strongly advised to always set bit14 to 1 to select PAL.
  • As components use partial address decoding, it is therefore possible to send the same value to different components simultaneously by carefully using custom I/O ports.


Memory Mapped I/O Ports

Mem Decoded as Port Read Write
#4000-7FFF %01xxxxxx xxxxxxxx ASIC - CPC+/GX4000 registers Read Write

See the ASIC page for details.


Related pages

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