Changes
Z80
,/* Alphabetical list */
|ADD IY, BC||15||2||rowspan=4|--?- 0 *||FD 09||rowspan=4|Add (IY register)||rowspan=4|IY = IY + rr
|-
|ADD IY, DE||15||2||FD 19
|-
|ADD IY, IY||15||2||FD 29
|DAA||4||1||***P-*||27||Decimal Adjust Acc.||A=BCD format (dec.)
|- style="background:#efefef;"
|DEC A||4||1||rowspan=10|***V1-||3D||rowspan=10|Decrement (8-bit)||rowspan=107|s=s-1
|-
|DEC B||4||1||05
|DEC L||4||2||2D
|-
|DEC (HL)||11||1||35||(HL)=(HL)-1
|-
|DEC (IX+N)||23||3||DD 35 XX||rowspan=2|(xx-d)=(xx-d)+1
|-
|DEC (IY+N)||23||3||FD 35 XX
|IN L,(C)||12||2||ED 68
|- style="background:#efefef;"
|INC A||4||1||rowspan=710|***V0-||3C||rowspan=710|Increment (8-bit)||rowspan=7|r=r+1
|- style="background:#efefef;"
|INC B||4||1||04
|- style="background:#efefef;"
|INC L||4||1||2C
|-
|INC (HL)||11||1||34||(HL)=(HL)+1
|- style="background:#efefef;"
|INC (IX+N)||23||3||DD 34 XX||rowspan=2|(xx+d)=(xx+d)+1
|- style="background:#efefef;"
|INC (IY+N)||23||3||FD 34 XX
|-
|INC BC||6||1||rowspan=4|------||03||rowspan=4|Increment (16-bit)||rowspan=4|ss=ss+1
|- style="background:#efefef;"
|INC IY||10||2||FD 23
|-
|IND||16||2||?*??1-||ED AA||Input and Decrement||(HL)=(C),HL=HL-1,B=B-1
|
|-
|CCF/SCF
|1
|1
|
|-
|CPD/CPI
|4
|2
|
|-
|CPDR/CPIR
|6/4
|2
|
|
|-
|DEC /INC (HL)
|3
|1
|
|-
|DEC /INC (IX/IY+d)
|6
|3
|
|-
|DEC /INC A/B/C/D/E/H/L
|1
|1
|
|-
|DEC /INC HX/LX/HY/LY
|2
|2
|
|-
|DEC /INC BC/DE/HL/SP
|2
|1
|
|-
|DEC /INC IX/IY
|3
|2
|
|-
|DI/EI
|1
|1
|4/3
|2
|
|-
|
|-
|5
|2
|
|-
|INDR/INIR
|6/5
|2
|
|-
|JP (HL)
|1
|1
|
|-
|JP (IX/IY)
|2
|2
|
|-
|LD I, A / LD A, I/R
|3
|2
|
|-
|LD I/R, A / LD A, R
|3
|2
|
|-
|LDD/LDI
|5
|2
|
|-
|LDDR|6/5|2||-|LDI|5|2||-|LDIR
|6/5
|2
|1
|
|-
|OUT (C), A/B/C/D/E/H/L
|3
|-
|OUTD/OUTI
|5
|2
|5*
|-
|OUTIOTDR/OTIR|6/5
|2
|5*
|
|-
|RES /SET x, (HL)
|4
|2
|
|-
|RES /SET x, (IX/IY+d)
|7
|4
|
|-
|RES /SET x, (IX/IY+d), A/B/C/D/E/H/L
|7
|4
|
|-
|RES /SET x, A/B/C/D/E/H/L
|2
|2
|
|-
|RETI/RETN
|4
|2
|
|-
|RETNRL/RLC/RR/RRC/SLA/SLL/SRA/SRL (HL)
|4
|2
|
|-
|RL (HL)|4|2||-|RL /RLC/RR/RRC/SLA/SLL/SRA/SRL (IX/IY+d)
|7
|4
|
|-
|RL /RLC/RR/RRC/SLA/SLL/SRA/SRL (IX/IY+d), A/B/C/D/E/H/L
|7
|4
|
|-
|RL /RLC/RR/RRC/SLA/SLL/SRA/SRL A/B/C/D/E/H/L
|2
|2
|
|-
|RLA/RLCA/RRA/RRCA
|1
|1
|
|-
|5
|2
|4
|1
|
|}
*x=[0..7], d=[0..ff], m=[0..2], aa=[0..ffff], a=[0..ff]
* * Some exceptions exist
* All instructions containing (IX/IY+d) add 3µs and 2 bytes compared to their (HL) variants
* Contrarily to what the syntax of the instructions JP (HL/IX/IY) suggest, PC will be loaded with the contents of the register itself, not the indexed value. Those instructions should be understood as JP HL/IX/IY
[[Category:Hardware]][[Category:Programming]][[Category:Datasheet]][[Category:CPC Internal Components]]
