Changes
/* Green Screen Colours */
*If interrupts are not authorized, then the R52 counter continues to increment and the interrupt remains armed (the Gate Array then maintains its INT signal). When interrupts are enabled (using the EI instruction) and '''after the instruction that follows EI''' (so not immediately after EI), bit5 of R52 is cleared and the interrupt takes place
== CSYNC signal ==
On CPC, the HSYNC and VSYNC signals are received from the [[CRTC]]. These signals are then modified and merged by the Gate Array into a single CSYNC signal that will be sent to the display.
When CRTC HSYNC is active, the Gate Array immediately outputs the palette colour black. If the HSYNC is set to 14 characters then black will be output for 14µs.
If a graphics mode change is pending, the HSYNC pulse width needs to be at least 2µs for Gate Array to change the graphics mode. The HSYNC is modified before being sent to the monitor. It only happens after 2µs after activation of the CRTC HSYNC and stay a maximum of 4µs(signal is cut short if HSYNC width is greater than 6).
For example, if CRTC R2=46, and CRTC HSYNC width is 14 chars then monitor hsync starts at 48 and lasts only until 51 included.
The same logic applies to VSYNC, with lines instead of chars. The Gate Array VSYNC is also modified before being sent to considered complete when the monitor26th line has been processed. It happens two lines* after Then the VSYNC from Gate Array stops outputting the CRTC and stay two lines (same cut rule if VSYNC is lower than 4). PAL (50Hz) does need two lines VSYNC_width, and 4µs HSYNC_widthpalette colour black.
The Gate Array uses 2 internal counters to create its CSYNC signal:
* H06 which counts the number of CRTC characters processed during an HSYNC. H06 is incremented by the Gate Array for each CRTC character when CRTC HSYNC is active. The Gate Array activates the C-HSYNC signal when H06 reaches 2, and changes its graphics mode if a change was pending. It deactivates this signal when H06 reaches 6.* V26 which counts the number of HSYNCs occuring during a VSYNC. V26 is incremented by the Gate Array when the CRTC signals an end of HSYNC. The Gate Array activates the C-VSYNC signal when V26 reaches 2. It deactivates this signal when V26 reaches 6. The HSYNC signal from the CRTC is 0 when inactive and 1 when active. Same for VSYNC. C-HSYNC and C-VSYNC are composited using the XNOR function. The resulting CSYNC signal produced by the Gate Array is 1 when inactive and 0 when active.
On a CPC monitor, the CSYNC is rendered in "absolute black". It is darker than the palette colour black output by the Gate Array.
== Register 3 - RAM Banking ==
This register exists only in CPCs with 128K RAM (like the CPC 6128, or CPCs with [[Standard Memory Expansions]]). Note: In the CPC 6128, the register is a separate [[PAL16L8|PAL chip]] that assists the Gate Array chip. See its wiki page.
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=== Green Screen Colours ===
On a green screen (where all colours are shades of green), the colours (in the software/firmware BASIC colours), are in order of increasing intensity. Black is very dark, and white is bright green, and colour 13 is a medium green. (Thanks to [[Mark Rison|Mark Rison]] for this information) The luminance (Y) is not exactly correlated to the actual luminance of colour images broadcast in RGB. We have other values. Amstrad preferred to propose a completely different image system, not comparable to a conversion to monochrome, which would have limited the number of brightness levels to 21 (for example, colours 9 and 6 would have had the same luminance). They opted for a table of 27 linear brightness steps. They assigned values of 1 (1kΩ) for blue, 3 (3.3kΩ) for red, and 9 (10kΩ) for green.
== Pictures ==
