Changes

Also designated as Video gate Array (VGA, not to be confused with IBM PC compatible graphic card spec).

== Introduction ==

The Gate Array is described here is the one found in a standard CPC.

== What does it do? ==

The Gate Array is responsible for the display (colour palette, resolution, horizontal and vertical sync), interrupt generation and memory arrangement.

== Interrupt management ==

*If the interrupts were authorized at the time of the request, then bit5 of R52 is cleared (but R52 was reset to 0 anyway) and the interrupt takes place

*If interrupts are not authorized, then the R52 counter continues to increment and the interrupt remains armed (the Gate Array then maintains its INT signal). When interrupts are enabled (using the EI instruction) and '''after the instruction that follows EI''' (so not immediately after EI), bit5 of R52 is cleared and the interrupt takes place

== CSYNC signal ==

On a CPC monitor, the CSYNC is rendered in "absolute black". It is darker than the palette colour black output by the Gate Array.

== Controlling the Gate Array ==

| 0 || x

|}

== Register 1 - Palette Data (Colour selection) ==

| 0 || x

|}

== Register 2 - Select screen mode and ROM configuration ==

| 0 || x

|}

== Register 3 - RAM Banking ==

The Video RAM is always located in the first 64K, VRAM is in no way affected by this register.

== Programming the Gate Array - Examples ==

ret

</pre>

== Video memory structure ==

|2 pixels in 4 colors

|}

== Split rasters ==

To easily make split rasters compatible with both the CPC and the Plus machines, one can use the ASIC soft-scroll control register (SSCR) to finely adjust the horizontal position of the graphics.

== Palette R,G,B definitions ==

They opted for a table of 27 linear brightness steps. They assigned values of 1 (1kΩ) for blue, 3 (3.3kΩ) for red, and 9 (10kΩ) for green.

== Pictures ==

Image:40226_am4_metal.jpg|40226 PreASIC Metal Layer

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==See also==