The ASIC provides an interrupt vector on interrupt request.
The register IVR (at address 6805h) supplies the top 5 bits of the vector. It is undefined at reset except that bit0 will be set to 1. Therefore, before placing the CPU in vectored interruptmode, always set up the IVR so that the top 5 bits are defined.
Bits2..1 of the interrupt vector provided by the ASIC to the CPU are as follows: 00 = DMA chan 2, 01 = DMA chan 1, 10 = DMA chan 0, 11 = DMA raster.