Changes
/* Instruction timing : talk about r005.8.16c29 */
==== Instruction timing : talk about r005.8.16c29 ====
This version does implements correctly a theorical WAIT_n generator : I used a script comparing Z80 doc timings to plustest.dsk testbench result on real CPC, I deduce that inserting each time 2 WAIT_n does the stuff(that will my first approach), I saw also that first set of instruction timing is fully covered by Z80 doc, so plustest. dsk testbench failing on this part is not due to table slowing down instruction timing (WAIT_n generator's table of slowing down instruction timing), this isntructioon have to be slowed somewhere else : perhaps a bug inside Z80 itself or else the equation NOP/HALT/ACK to review, instructions concerned here seems all about "JUMP" except two instruction (a LD and an EX), in past I did already tested Z80 instruction timing themself and found no problem this way. I also revisited the edges of WAIT_n generator, to insert WAIT_n at 2T.
I also removed the edge detection of IO_ACK on gatearray, replacing it by state detection of IO_ACK, resulting cpctest's testbench back : this test of HSYNC width is now successfull.