Changes
/* Some bad instruction timing analysis */
| 02 || LD (BC), A || 2 || || 3 || Fixed on r005.8.16c3
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| 10 || DJNZ, e || 4/3 || 4/2 || 4/2|| T States begin by "(5, " : M1 is longer than 4. Seems adding also one Wait_n in this case (as about MEM_wr)
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| 12 || LD (DE), A || 2 || || 3 || Fixed on r005.8.16c3
| C5 || PUSH bc || 4 || 3 || || PUSH qq (same as F5), ok using MEM_wr:low
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| C7 || RST 00h || 4 || 3 || 3 || RST p. Fixed on r005.8.16c3. T States begin by "(5, " : M1 is longer than 4.
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| C8 || RET z || 4/2 || 3/2 || 3/2 || RET cc, it seems correct following doc: true@5+3+3=>3*4; false@5=>2*4. Damn. T States begin by "(5, " : M1 is longer than 4.
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| CC || || 5/3 || 5/3 || 6/3 || Fixed on r005.8.16c3
| CD || || 5 || || 6 || Fixed on r005.8.16c3
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| CF || RST 08h || 4 || 3 || 3 || RST p. Fixed on r005.8.16c3
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| D0 || RET nc || 2/4 || 2/3 || 2/3 || RET cc, inverse of RET c.
| D5|| PUSH de || 4 || 3 || || PUSH qq (same as F5), ok using MEM_wr:low
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| D7 || RST 10h || 4 || 3 || 3 || RST p. Fixed on r005.8.16c3
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| D8 || RET c || 4/2 || 3/2 || 3/2 || RET cc
| DC || || 5/3 || || 6/3 || Fixed on r005.8.16c3
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| DF || RST 18h || 4 || 3 || 3 || RST p. Fixed on r005.8.16c3
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| E0 || RET po || 2/4 || 2/3 || 2/3 || RET cc, inverse of RET pe.
| E5 || PUSH hl || 4 || 3 || PUSH qq (same as F5), ok using MEM_wr:low
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| E7 || RST 20h || 4 || 3 || 3 || RST p. Fixed on r005.8.16c3
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| E8 || RET pe || 4/2 || 3/2 || 3/2 || RET cc
| EC || || 5/3 || || 6/3 || Fixed on r005.8.16c3
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| EF || RST 28h || 4 || 3 || 3 || RST p. Fixed on r005.8.16c3
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| F0 || RET p || 2/4 || 2/3 || 2/3 || RET cc, inverse of RET m.
| F5 || PUSH af || 4 || 3 || || PUSH qq, 5+3+3=11<3*4, is MEM_WR prologation effective two times here 1T+1T ? yes : pushing a register pair here, ok using MEM_wr:low
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| F7 || RST 30h || 4 || 3 || 3 || RST p. Fixed on r005.8.16c3
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| F8 || RET m || 4/2 || 3/2 || 3/2 || RET cc
| FC || || 5/3 || || 6/3 || Fixed on r005.8.16c3
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| FF || RST 38h || 4 || 3 || 3 || RST p. Fixed on r005.8.16c3.
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