Changes
/* TODO : Z80 testbench */
[http://www.winape.net/download/plustest.zip WinAPE plustest.zip (including Instruction and Interrupt timing tests)]
===== Z80 architecture : T80.vhdl =====
17 pages of source codes to read.
Not analyzed yet completly.
Contains the main workflow of Z80: current MCycle and its current TState.
Contains T80_ALU.vhdl and T80_MCode.vhdl components.
===== Z80 architecture : T80_ALU.vhdl =====
6 pages of source codes to read.
Not analyzed yet completly. This analyse can certainly be wrong : wip.
Contains flags : C N P X H Y Z S
C : carry - set if result did not fit in the register
N : negative? - last instruction was substract
P : parity or overflow - overflow example : signed, 7F+7F=FE with overflow setted
X : undocumented
H : half carry - set if 4bit first bits of result did not fit in the register
Y : undocumented
Z : zero - set if result is zero
S : sign - it is an input ?
Contains ALU_Op : [ADD ADC SUB SBC AND XOR OR CP] ROT BIT [SET RES] DAA
ALU_Op is the basic instructions of Z80 coded here. T80_ALU.vhdl is a slave, a service exposed to T80_MCode.vhdl throw T80.vhdl
===== Z80 architecture : T80_MCode.vhdl =====
First 5 pages, and last 2 pages of source codes to read. Others pages are "always the same" architectually speaking.
Gives instruction lengh : MCycles, TStates (please remark the 's' at end of theses words...)
It's a "controler", does gives orders to T80_ALU.vhdl throw T80.vhdl
Actions of this controler are :
* ALU_Op : the action !
* I_DJNZ I_CPL I_CCF I_SCF I_RETN I_BT I_BC I_BTR I_RLD I_RRD I_INRC : actions not for ALU (wiring input/ouput, changing flags...)
* Save_ALU/PreserveC : an option about register "erased or not" at next instruction
Instructions not coded in T80_MCode.vhdl but in T80.vhdl (strange, barbarian part of code ?) :
* Jump/E/XY Call RstP LDZ LDW LDSPHL Special_LD ExchangeDH/Dp/AF/RS
=== Alignment of HSYNC Interrupt ===
