Changes
/* Technical */
== Technical ==
The standard expansions are based on the RAM banking logic from the CPC6128, ie. equivalent This is handled by a PAL16L8 but to the programmer it appears to be the fourth register in the [[Gate Array]] register in . The I/O decoding is different to the CPC6128 (or more preciselyGate-Array.* PAL16L8 decodes A15=0 only* Gate-Array decodes A15=0 and A14=1 To access the RAM and Gate-Array port 7fxx is used. In addition the RAM answers when the data has bit 7=1 and bit 6=1, which is unused in the PAL that assists its Gate -Array chip). External expansions have their own PAL or hardware which performs the same operation. Later CPC revisions with the costdown ASIC and the Plus have the RAM expansion logic inside their ASICs.
----
=== Standard 128K-512K Expansions (dk'tronics/dobbertin-style) ===
Expansions bigger than 64K combine the CPC6128-style mapping with some formerly unused chips bits in the fourth Gate Array registervalue written to the RAM select:
5-3 Bank number in 64K units (for expansions bigger than 64K) (max = 512K)
'''Caution''' - The 64K bank numbers don't always start at bank 0 (In the Dk'tronics 256K Silicon Disc, the 64K banks are numbered 4..7).
aaa = upper bits of 64K bank selection (512K-step) (A8,A9,A10 bits)
bbb = lower bits of 64K bank selection (64K-step) (D3,D4,D5 bits)
xxxxxxxx = should be set so that it doesn't conflict with other ports (*)
(*) For example 7B01h or 7B7Fh would be no good, because the FDC commandregister at FB7Fh is mirrored to these locations. Using 7B80h..7BFFh wouldfix that problem, but might conflict with other connected expansionhardware.
* '''Compatibility''' - The first 512K (Port 7Fxxh) are fully compatible with dk'tronics. Using the next 1.5MB (Port 7Exxh,7Dxxh,7Cxxh) should work without conflicting with the other hardware expansions.