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VHDL

1 byte added, 14:00, 5 March 2017
end if;
All instruction are runs at the same time/edge. Next values being computed from previous values. The time an output value take takes to be affected by input value is called "delta-time". Like in "This cannot run !, you forgotten that it takes 4 delta-time to cross this 4 components !!!". There is a difference between delta time and number of clock edge, as certain components are rising_edge and others are falling_edge. delta-time is just about vocabulary speaking, it the time between the action is launched and then take effect outside. In order to understood this concept, better is to play using "testbench" programs, showing sequence diagrams.
You can also have local registered value, using affectation operator ":=", without delta-time (at once) :
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