Changes
=== Instruction timing ===
I tested instruction timing of [[T80]] compare to instruction timing of JavaCPC emulator. I deduce synchronization of Z80 with CRTC on M1 signal by WAIT_n insertion in order to have a multiple of 4 Tstates per instruction. I deduce also one WAIT_n inserted during MEM_WR operation (yes I log testbench [[T80]], Iām crazy)
I just made a test bench log of [[T80 ]] (log of instruction's M1, and first M1 coming after knowing that I send a lot of NOP after my instruction), and compare it to a JavaCPC timing array. Some instructions was not tested (interrupt wait, and special timing (instructions with change timing)), but all others passed correctly.
==== Instruction timing : currently in r008.5.14 ====
For it I plug all wires simply from 1 to 40. Some wires are cut, some are Vcc, others GND. Z80 output are directly connected, Z80 input are pull-up with red-red-red resistors (I like red), Z80 is powered 5v (pmod can give 5v using jumper). In fact z80 is so old component that powering it 5v do output 3.3v.
In fact the only difference between [[T80 ]] of opencore and real Z80 is that [[T80 ]] run on rising_edge, and Z80 run during low state. Test past with little modification of sequencer forcing it do nothing during low state of z80, resulting a downclock (memory is too overclocked with this sequencer modification), perhaps using buffer on address bus and data bus could solve this detail... but as it runs for me it is not a problem.
==== TODO : Z80 testbench ====
==== FPGA internal RAM size ====
It's to know that a FPGA chip contain 45KB internal RAM (360Kb for NEXYS2 500k-gates, and 504Kb for 1200k-gates) so you can't insert a dsk inside. This internal RAM is already used in part by [[T80 ]] (z80 from opencores), by the soundchip, and for special RAM '''ramb16_s16_s16''' (RAM with two different speed one for writing another for reading, in fact two RAM with a common part) that I use for VGA mode.
==== VHDL components size ====
[[T80 ]] (z80 processor) take 100kgates
Yamaha sound chip (from fpgaarcade) take 50kgates
== Components ==
sound chip is [http://www.fpgaarcade.com/library.htm [ym2149 fpgaarcade]] one, patched, and repatched in order to get stereo sound.
PPI chip is [http://www.cpcwiki.eu/index.php/VHDL_implementation_of_the_8255_PIO 8255 CPCWiki] one, patched.
Secondary Steve Ciarca, author of "Build your own Z80 computer" (1981), so nice book.
Then the author of the VHDL version of Yamaha sound chip : [http://www.fpgaarcade.com/library.htm fpgaarcade]. And [http://opencores.org/project,t80 opencores] for the Z80 ([[T80]])...
And websites that give access to so much old Amstrad resources like :
