Changes

WARRANTY: There is no warranty of any defects of your CPC!!! On my CPC everything works fine '''Bugs and I hope that you wonConfusing things in the GIF schematic:'t have any problems with this RS232''* Confusing: Signals 0..15 on the left side of the schematic refer to address lines A0..A15* Bug: Z80-InterfaceSTI Pin 3 (TCO) should be wired to Pin 39 (RC), not to Pin 34 (A1).

Z80-STI: 50 to 19200 bps (5,6,7 or 8 bit, 1, 1 1/2, 2 stopb.stopbits, all parity flags) 24 registers, use 16 registers (direct) with F8E0-F8EF, the last 8 registers can be used indirect with a special register

== The meaning and the adresses Addresses of the registers:==

register === Register 0, port adress F8E0:(Port F8E0h) Indirect Data ===

register === Register 1, port adress F8E1:(Port F8E1h) Handshake signals ===This register transfer transfers the data from and to the I/O port of the chip. If youuse V24 you can request handshake signals from this port. In this interfacethe following bits have this meaning: Bit 0: DTR (Data Terminal Ready) Bit 1: RTS (Ready to Send) Bit 2: CTS (Clear to Send) Bit 3: DSR (Data Set Ready) Bit 4-7: not used

register === Register 2-7, port adress F8E2(Port F8E2h-F8E7:F8E7h) Interrupt related ===

register === Register 8, port F8E8:(Port F8E8h) Indirect Index ===Bit 3-7 are used by the interrupt handler. With bit 0-2 you can choose theindirect register.

register === Register 9, port adress F8E9:(Port F8E9h) Timer Controls ===Controll Control register for timer A and B. You needn't to use the timer for a V24interface.

register === Register 10, port adress F8EA:(Port F8EAh) Timer B ===

register === Register 11, port adress F8EB:(Port F8EBh) Timer A===

register === Register 12, port adress F8EC:(Port F8ECh) Mode Control ===

register === Register 13, port adress F8ED:(Port F8EDh) Rx Status ===

Bit 0: Receiver-Enable, set to 1 if receiving is possible.Bit 1: Memory full "1" or not "0". === Register 14 (If 8 Bits are received then the interface send memory fullPort F8EEh). register 14, port adress F8EE:Tx Status ===

Bit 0: Sending-Enable, must set to "1" if sending is allowed.Bit 7: Memory full "1" or not "0". This bit can be used to ask if a word is send or not. register === Register 15, port adress F8EF:(Port F8EFh) Rx/Tx Data ===

== Indirect registers (Choose them with register 8):==

For more exact informations please write to Mostek and ask for support for theZ80-STI. You also can look at the assembler code. 

Number of bps: 0 = 50 bps 1 = 75 bps 2 = 110 bps 3 = 150 bps 4 = 300 bps 5 = 600 bps 6 = 1200 bps 7 = 2400 bps Number of stop bits: 1 = 1 stop bit 0 = 2 stop bit Data bits: 0 = 7 data bits 1 = 8 data bits Parity even/odd: 1 = even 0 = odd Parity on/off: 1 = on 0 = off

0 = 50 Normally, you use 8N1 for connection with BBS's you can initialise this with |FORMAT, number of bps , 1 = 75 bps 2 = 110 bps 3 = 150 bps 4 = 300 bps 5 = 600 bps 6 = 1200 bps 7 = 2400 bps, 1, 0, 1.

Data bits: 0 = 7 data bits1 = 8 data bits Parity: 1 = even0 = odd Parity: 1 = on0 = off Normally, you use 8N1 for connection with BBS's you can initialise this with|FORMAT, number of bps, 1, 1, 0, 1.  '''|RECORD'''SEND, @a$The incoming chars will be read in a string. Control codes will be send to thestring, too, because sometimes you need it for binary transmissions.  '''|SEND''', @a$- The string is send until it ends, except you press ESC. The program will notsend CR or LF, so you can use this for binary transmission.  == Last words == This interface is described in the book "Maschinenspracheprogramm und Hardware-erweiterungen fuer Schneider CPC's" from the IDEA Verlag. I hope that every-thing is ok with the circuit plans and that you don't have a broken CPC whenyou use it ;-). Sorry for bad english. (Please help me to find my faults). If something in my circuit plan is not ok please write to Tim Riemann Gartenweg 3 35114 Haina-Kloster Germany eMail: TCS-Software@t-online.de

1-* 1x [[Media:Mostek_3801_Data.pdf|Z80-STI (or MK 3801MK3801-4) ]]* 1x SN75189 - RS232 to TTL level shifter* 1x SN75188 - TTL to RS232 level shifter* 1x 74LS30 - Single 8-input NAND gate* 1x 74LS138 - 1-of-8 inverting decoder/demultiplexer* 1x 74LS20 - Dual 4-input NAND gates* 1x 74LS04 - Hex Inverters* 1x 74LS32 - Quad 2-input OR gates* 1x 25pin SUB-D connector (male)* 1x connector for the [[Connector:Expansion_port|expansion port]]Note: The 74LS20, 74LS04, 74LS32 are the smaller logic symbols in the schematic.