Changes
/* Usage in CPC interfaces */
F4X3h Aleste PPI Port A, Timer 0-2 Control Registers (W)
Clock Input for RX/TX is 4MHz, Clock output goes to a [[8251 USART chip]],
Clock Output may be further divided by 1, 16, or 64 in the 8251 chip,
Clock Input for FUTURE is HSYNC, Clock output selects 1st/2nd color set,
the FUTURE clock is restarted via GATE=[[CRTC]]'s "CURSOR" output, All registers are write-only (the 8251 chips /RD is wired to VCC)
PPI Port A data direction must be output,
Aleste ExtReg must enable access to 8253, and disable access to PSG
