Changes
/* Aleste ROMRAM prom (Gate Array 2, ROM/RAM enable) */
0080: B 7 B 7 7 7 7 7 7 7 7 7 B B 7 7 ;\
0090: B 7 B 7 7 7 7 7 7 7 7 7 B B 7 7 ;
00A0: F F F F F F F F F F F F F F F F ; same as similar to above, but with bit0 = always set
00B0: F F F F F F F F F F F F F F F F ; (internal RAM forcefully disabled via
00C0: F F F F F F F F F F F F F F F F ; RAMDIS signal from expansion port)
00D0: F F F F F F F F F F F F F F F F ; ... hmm, he "B" and "7" values do what exactly ?
00E0: F F F F F F F F F F F F F F F F ;
00F0: F F F F F F F F F F F F F F F F ;/
